1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _ASM_GT64120_H 20 #define _ASM_GT64120_H 21 #include <linux/clocksource.h> 22 #include <asm/addrspace.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <asm/byteorder.h> 25 #define MSK(n) ((1 << (n)) - 1) 26 #define GT_CPU_OFS 0x000 27 #define GT_MULTI_OFS 0x120 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define GT_SCS10LD_OFS 0x008 30 #define GT_SCS10HD_OFS 0x010 31 #define GT_SCS32LD_OFS 0x018 32 #define GT_SCS32HD_OFS 0x020 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define GT_CS20LD_OFS 0x028 35 #define GT_CS20HD_OFS 0x030 36 #define GT_CS3BOOTLD_OFS 0x038 37 #define GT_CS3BOOTHD_OFS 0x040 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define GT_PCI0IOLD_OFS 0x048 40 #define GT_PCI0IOHD_OFS 0x050 41 #define GT_PCI0M0LD_OFS 0x058 42 #define GT_PCI0M0HD_OFS 0x060 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define GT_ISD_OFS 0x068 45 #define GT_PCI0M1LD_OFS 0x080 46 #define GT_PCI0M1HD_OFS 0x088 47 #define GT_PCI1IOLD_OFS 0x090 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define GT_PCI1IOHD_OFS 0x098 50 #define GT_PCI1M0LD_OFS 0x0a0 51 #define GT_PCI1M0HD_OFS 0x0a8 52 #define GT_PCI1M1LD_OFS 0x0b0 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define GT_PCI1M1HD_OFS 0x0b8 55 #define GT_PCI1M1LD_OFS 0x0b0 56 #define GT_PCI1M1HD_OFS 0x0b8 57 #define GT_SCS10AR_OFS 0x0d0 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define GT_SCS32AR_OFS 0x0d8 60 #define GT_CS20R_OFS 0x0e0 61 #define GT_CS3BOOTR_OFS 0x0e8 62 #define GT_PCI0IOREMAP_OFS 0x0f0 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define GT_PCI0M0REMAP_OFS 0x0f8 65 #define GT_PCI0M1REMAP_OFS 0x100 66 #define GT_PCI1IOREMAP_OFS 0x108 67 #define GT_PCI1M0REMAP_OFS 0x110 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define GT_PCI1M1REMAP_OFS 0x118 70 #define GT_CPUERR_ADDRLO_OFS 0x070 71 #define GT_CPUERR_ADDRHI_OFS 0x078 72 #define GT_CPUERR_DATALO_OFS 0x128 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define GT_CPUERR_DATAHI_OFS 0x130 75 #define GT_CPUERR_PARITY_OFS 0x138 76 #define GT_PCI0SYNC_OFS 0x0c0 77 #define GT_PCI1SYNC_OFS 0x0c8 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define GT_SCS0LD_OFS 0x400 80 #define GT_SCS0HD_OFS 0x404 81 #define GT_SCS1LD_OFS 0x408 82 #define GT_SCS1HD_OFS 0x40c 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define GT_SCS2LD_OFS 0x410 85 #define GT_SCS2HD_OFS 0x414 86 #define GT_SCS3LD_OFS 0x418 87 #define GT_SCS3HD_OFS 0x41c 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define GT_CS0LD_OFS 0x420 90 #define GT_CS0HD_OFS 0x424 91 #define GT_CS1LD_OFS 0x428 92 #define GT_CS1HD_OFS 0x42c 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define GT_CS2LD_OFS 0x430 95 #define GT_CS2HD_OFS 0x434 96 #define GT_CS3LD_OFS 0x438 97 #define GT_CS3HD_OFS 0x43c 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define GT_BOOTLD_OFS 0x440 100 #define GT_BOOTHD_OFS 0x444 101 #define GT_ADERR_OFS 0x470 102 #define GT_SDRAM_CFG_OFS 0x448 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define GT_SDRAM_OPMODE_OFS 0x474 105 #define GT_SDRAM_BM_OFS 0x478 106 #define GT_SDRAM_ADDRDECODE_OFS 0x47c 107 #define GT_SDRAM_B0_OFS 0x44c 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define GT_SDRAM_B1_OFS 0x450 110 #define GT_SDRAM_B2_OFS 0x454 111 #define GT_SDRAM_B3_OFS 0x458 112 #define GT_DEV_B0_OFS 0x45c 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define GT_DEV_B1_OFS 0x460 115 #define GT_DEV_B2_OFS 0x464 116 #define GT_DEV_B3_OFS 0x468 117 #define GT_DEV_BOOT_OFS 0x46c 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define GT_ECC_ERRDATALO 0x480 120 #define GT_ECC_ERRDATAHI 0x484 121 #define GT_ECC_MEM 0x488 122 #define GT_ECC_CALC 0x48c 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define GT_ECC_ERRADDR 0x490 125 #define GT_DMA0_CNT_OFS 0x800 126 #define GT_DMA1_CNT_OFS 0x804 127 #define GT_DMA2_CNT_OFS 0x808 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define GT_DMA3_CNT_OFS 0x80c 130 #define GT_DMA0_SA_OFS 0x810 131 #define GT_DMA1_SA_OFS 0x814 132 #define GT_DMA2_SA_OFS 0x818 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define GT_DMA3_SA_OFS 0x81c 135 #define GT_DMA0_DA_OFS 0x820 136 #define GT_DMA1_DA_OFS 0x824 137 #define GT_DMA2_DA_OFS 0x828 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define GT_DMA3_DA_OFS 0x82c 140 #define GT_DMA0_NEXT_OFS 0x830 141 #define GT_DMA1_NEXT_OFS 0x834 142 #define GT_DMA2_NEXT_OFS 0x838 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define GT_DMA3_NEXT_OFS 0x83c 145 #define GT_DMA0_CUR_OFS 0x870 146 #define GT_DMA1_CUR_OFS 0x874 147 #define GT_DMA2_CUR_OFS 0x878 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define GT_DMA3_CUR_OFS 0x87c 150 #define GT_DMA0_CTRL_OFS 0x840 151 #define GT_DMA1_CTRL_OFS 0x844 152 #define GT_DMA2_CTRL_OFS 0x848 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define GT_DMA3_CTRL_OFS 0x84c 155 #define GT_DMA_ARB_OFS 0x860 156 #define GT_TC0_OFS 0x850 157 #define GT_TC1_OFS 0x854 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define GT_TC2_OFS 0x858 160 #define GT_TC3_OFS 0x85c 161 #define GT_TC_CONTROL_OFS 0x864 162 #define GT_PCI0_CMD_OFS 0xc00 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define GT_PCI0_TOR_OFS 0xc04 165 #define GT_PCI0_BS_SCS10_OFS 0xc08 166 #define GT_PCI0_BS_SCS32_OFS 0xc0c 167 #define GT_PCI0_BS_CS20_OFS 0xc10 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define GT_PCI0_BS_CS3BT_OFS 0xc14 170 #define GT_PCI1_IACK_OFS 0xc30 171 #define GT_PCI0_IACK_OFS 0xc34 172 #define GT_PCI0_BARE_OFS 0xc3c 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define GT_PCI0_PREFMBR_OFS 0xc40 175 #define GT_PCI0_SCS10_BAR_OFS 0xc48 176 #define GT_PCI0_SCS32_BAR_OFS 0xc4c 177 #define GT_PCI0_CS20_BAR_OFS 0xc50 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define GT_PCI0_CS3BT_BAR_OFS 0xc54 180 #define GT_PCI0_SSCS10_BAR_OFS 0xc58 181 #define GT_PCI0_SSCS32_BAR_OFS 0xc5c 182 #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 #define GT_PCI1_CMD_OFS 0xc80 185 #define GT_PCI1_TOR_OFS 0xc84 186 #define GT_PCI1_BS_SCS10_OFS 0xc88 187 #define GT_PCI1_BS_SCS32_OFS 0xc8c 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 #define GT_PCI1_BS_CS20_OFS 0xc90 190 #define GT_PCI1_BS_CS3BT_OFS 0xc94 191 #define GT_PCI1_BARE_OFS 0xcbc 192 #define GT_PCI1_PREFMBR_OFS 0xcc0 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 #define GT_PCI1_SCS10_BAR_OFS 0xcc8 195 #define GT_PCI1_SCS32_BAR_OFS 0xccc 196 #define GT_PCI1_CS20_BAR_OFS 0xcd0 197 #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 200 #define GT_PCI1_SSCS32_BAR_OFS 0xcdc 201 #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 202 #define GT_PCI1_CFGADDR_OFS 0xcf0 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 #define GT_PCI1_CFGDATA_OFS 0xcf4 205 #define GT_PCI0_CFGADDR_OFS 0xcf8 206 #define GT_PCI0_CFGDATA_OFS 0xcfc 207 #define GT_INTRCAUSE_OFS 0xc18 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define GT_INTRMASK_OFS 0xc1c 210 #define GT_PCI0_ICMASK_OFS 0xc24 211 #define GT_PCI0_SERR0MASK_OFS 0xc28 212 #define GT_CPU_INTSEL_OFS 0xc70 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define GT_PCI0_INTSEL_OFS 0xc74 215 #define GT_HINTRCAUSE_OFS 0xc98 216 #define GT_HINTRMASK_OFS 0xc9c 217 #define GT_PCI0_HICMASK_OFS 0xca4 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define GT_PCI1_SERR1MASK_OFS 0xca8 220 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 221 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 222 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c 225 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 226 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 227 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c 230 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 231 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 232 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 235 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 236 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 237 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 240 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 241 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c 242 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 245 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 246 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c 247 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 250 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 251 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c 252 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 255 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 256 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c 257 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 260 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 261 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 262 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 265 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 266 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 267 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c 270 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 271 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 272 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c 275 #define GT_CPU_ENDIAN_SHF 12 276 #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) 277 #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define GT_CPU_WR_SHF 16 280 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) 281 #define GT_CPU_WR_BIT GT_CPU_WR_MSK 282 #define GT_CPU_WR_DXDXDXDX 0 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define GT_CPU_WR_DDDD 1 285 #define GT_PCI_DCRM_SHF 21 286 #define GT_PCI_LD_SHF 0 287 #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define GT_PCI_HD_SHF 0 290 #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) 291 #define GT_PCI_REMAP_SHF 0 292 #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define GT_CFGADDR_CFGEN_SHF 31 295 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) 296 #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK 297 #define GT_CFGADDR_BUSNUM_SHF 16 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) 300 #define GT_CFGADDR_DEVNUM_SHF 11 301 #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) 302 #define GT_CFGADDR_FUNCNUM_SHF 8 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) 305 #define GT_CFGADDR_REGNUM_SHF 2 306 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) 307 #define GT_SDRAM_BM_ORDER_SHF 2 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) 310 #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK 311 #define GT_SDRAM_BM_ORDER_SUB 1 312 #define GT_SDRAM_BM_ORDER_LIN 0 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define GT_SDRAM_BM_RSVD_ALL1 0xffb 315 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 316 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) 317 #define GT_SDRAM_ADDRDECODE_ADDR_0 0 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define GT_SDRAM_ADDRDECODE_ADDR_1 1 320 #define GT_SDRAM_ADDRDECODE_ADDR_2 2 321 #define GT_SDRAM_ADDRDECODE_ADDR_3 3 322 #define GT_SDRAM_ADDRDECODE_ADDR_4 4 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 #define GT_SDRAM_ADDRDECODE_ADDR_5 5 325 #define GT_SDRAM_ADDRDECODE_ADDR_6 6 326 #define GT_SDRAM_ADDRDECODE_ADDR_7 7 327 #define GT_SDRAM_B0_CASLAT_SHF 0 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) 330 #define GT_SDRAM_B0_CASLAT_2 1 331 #define GT_SDRAM_B0_CASLAT_3 2 332 #define GT_SDRAM_B0_FTDIS_SHF 2 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) 335 #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK 336 #define GT_SDRAM_B0_SRASPRCHG_SHF 3 337 #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK 340 #define GT_SDRAM_B0_SRASPRCHG_2 0 341 #define GT_SDRAM_B0_SRASPRCHG_3 1 342 #define GT_SDRAM_B0_B0COMPAB_SHF 4 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) 345 #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK 346 #define GT_SDRAM_B0_64BITINT_SHF 5 347 #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK 350 #define GT_SDRAM_B0_64BITINT_2 0 351 #define GT_SDRAM_B0_64BITINT_4 1 352 #define GT_SDRAM_B0_BW_SHF 6 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) 355 #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK 356 #define GT_SDRAM_B0_BW_32 0 357 #define GT_SDRAM_B0_BW_64 1 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 #define GT_SDRAM_B0_BLODD_SHF 7 360 #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) 361 #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK 362 #define GT_SDRAM_B0_PAR_SHF 8 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) 365 #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK 366 #define GT_SDRAM_B0_BYPASS_SHF 9 367 #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK 370 #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 371 #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) 372 #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 #define GT_SDRAM_B0_SRAS2SCAS_2 0 375 #define GT_SDRAM_B0_SRAS2SCAS_3 1 376 #define GT_SDRAM_B0_SIZE_SHF 11 377 #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK 380 #define GT_SDRAM_B0_SIZE_16M 0 381 #define GT_SDRAM_B0_SIZE_64M 1 382 #define GT_SDRAM_B0_EXTPAR_SHF 12 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) 385 #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK 386 #define GT_SDRAM_B0_BLEN_SHF 13 387 #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK 390 #define GT_SDRAM_B0_BLEN_8 0 391 #define GT_SDRAM_B0_BLEN_4 1 392 #define GT_SDRAM_CFG_REFINT_SHF 0 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) 395 #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 396 #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) 397 #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define GT_SDRAM_CFG_RMW_SHF 15 400 #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) 401 #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK 402 #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) 405 #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK 406 #define GT_SDRAM_CFG_DUPCNTL_SHF 19 407 #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK 410 #define GT_SDRAM_CFG_DUPBA_SHF 20 411 #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) 412 #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define GT_SDRAM_CFG_DUPEOT0_SHF 21 415 #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) 416 #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK 417 #define GT_SDRAM_CFG_DUPEOT1_SHF 22 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) 420 #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK 421 #define GT_SDRAM_OPMODE_OP_SHF 0 422 #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 #define GT_SDRAM_OPMODE_OP_NORMAL 0 425 #define GT_SDRAM_OPMODE_OP_NOP 1 426 #define GT_SDRAM_OPMODE_OP_PRCHG 2 427 #define GT_SDRAM_OPMODE_OP_MODE 3 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define GT_SDRAM_OPMODE_OP_CBR 4 430 #define GT_TC_CONTROL_ENTC0_SHF 0 431 #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) 432 #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 #define GT_TC_CONTROL_SELTC0_SHF 1 435 #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) 436 #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK 437 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 440 #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK 441 #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 442 #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK 445 #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 446 #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) 447 #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define GT_PCI0_BARE_INTIODIS_SHF 3 450 #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) 451 #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK 452 #define GT_PCI0_BARE_INTMEMDIS_SHF 4 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) 455 #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK 456 #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 457 #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK 460 #define GT_PCI0_BARE_CS20DIS_SHF 6 461 #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) 462 #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define GT_PCI0_BARE_SCS32DIS_SHF 7 465 #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) 466 #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK 467 #define GT_PCI0_BARE_SCS10DIS_SHF 8 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) 470 #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK 471 #define GT_INTRCAUSE_MASABORT0_SHF 18 472 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK 475 #define GT_INTRCAUSE_TARABORT0_SHF 19 476 #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) 477 #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define GT_PCI0_CFGADDR_REGNUM_SHF 2 480 #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) 481 #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 482 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 485 #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) 486 #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 487 #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 490 #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) 491 #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK 492 #define GT_PCI0_CMD_MBYTESWAP_SHF 0 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) 495 #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK 496 #define GT_PCI0_CMD_MWORDSWAP_SHF 10 497 #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK 500 #define GT_PCI0_CMD_SBYTESWAP_SHF 16 501 #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) 502 #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define GT_PCI0_CMD_SWORDSWAP_SHF 11 505 #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 506 #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 507 #define GT_INTR_T0EXP_SHF 8 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) 510 #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK 511 #define GT_INTR_RETRYCTR0_SHF 20 512 #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK 515 #define GT_DEF_PCI0_IO_BASE 0x10000000UL 516 #define GT_DEF_PCI0_IO_SIZE 0x02000000UL 517 #define GT_DEF_PCI0_MEM0_BASE 0x12000000UL 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL 520 #define GT_DEF_BASE 0x14000000UL 521 #define GT_MAX_BANKSIZE (256 * 1024 * 1024) 522 #define GT_LATTIM_MIN 6 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 #include <mach-gt64120.h> 525 #define __GT_READ(ofs) (*(volatile u32 *)(GT64120_BASE+(ofs))) 526 #define __GT_WRITE(ofs, data) do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) 527 #define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) 530 #endif 531