1@c Copyright (C) 2000-2014 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4 5@ifset GENERIC 6@page 7@node ARC-Dependent 8@chapter ARC Dependent Features 9@end ifset 10 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter ARC Dependent Features 14@end ifclear 15 16@set ARC_CORE_DEFAULT 6 17 18@cindex ARC support 19@menu 20* ARC Options:: Options 21* ARC Syntax:: Syntax 22* ARC Floating Point:: Floating Point 23* ARC Directives:: ARC Machine Directives 24* ARC Opcodes:: Opcodes 25@end menu 26 27 28@node ARC Options 29@section Options 30@cindex ARC options (none) 31@cindex options for ARC (none) 32 33@table @code 34 35@cindex @code{-marc[5|6|7|8]} command line option, ARC 36@item -marc[5|6|7|8] 37This option selects the core processor variant. Using 38@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which 39is also the default. 40 41@table @code 42 43@cindex @code{arc5} arc5, ARC 44@item arc5 45Base instruction set. 46 47@cindex @code{arc6} arc6, ARC 48@item arc6 49Jump-and-link (jl) instruction. No requirement of an instruction between 50setting flags and conditional jump. For example: 51 52@smallexample 53 mov.f r0,r1 54 beq foo 55@end smallexample 56 57@cindex @code{arc7} arc7, ARC 58@item arc7 59Break (brk) and sleep (sleep) instructions. 60 61@cindex @code{arc8} arc8, ARC 62@item arc8 63Software interrupt (swi) instruction. 64 65@end table 66 67Note: the @code{.option} directive can to be used to select a core 68variant from within assembly code. 69 70@cindex @code{-EB} command line option, ARC 71@item -EB 72This option specifies that the output generated by the assembler should 73be marked as being encoded for a big-endian processor. 74 75@cindex @code{-EL} command line option, ARC 76@item -EL 77This option specifies that the output generated by the assembler should 78be marked as being encoded for a little-endian processor - this is the 79default. 80 81@end table 82 83@node ARC Syntax 84@section Syntax 85@menu 86* ARC-Chars:: Special Characters 87* ARC-Regs:: Register Names 88@end menu 89 90@node ARC-Chars 91@subsection Special Characters 92 93@cindex line comment character, ARC 94@cindex ARC line comment character 95The presence of a @samp{#} on a line indicates the start of a comment 96that extends to the end of the current line. Note that if a line 97starts with a @samp{#} character then it can also be a logical line 98number directive (@pxref{Comments}) or a preprocessor 99control command (@pxref{Preprocessing}). 100 101@cindex line separator, ARC 102@cindex statement separator, ARC 103@cindex ARC line separator 104The ARC assembler does not support a line separator character. 105 106@node ARC-Regs 107@subsection Register Names 108 109@cindex ARC register names 110@cindex register names, ARC 111*TODO* 112 113 114@node ARC Floating Point 115@section Floating Point 116 117@cindex floating point, ARC (@sc{ieee}) 118@cindex ARC floating point (@sc{ieee}) 119The ARC core does not currently have hardware floating point 120support. Software floating point support is provided by @code{GCC} 121and uses @sc{ieee} floating-point numbers. 122 123 124@node ARC Directives 125@section ARC Machine Directives 126 127@cindex machine directives, ARC 128@cindex ARC machine directives 129The ARC version of @code{@value{AS}} supports the following additional 130machine directives: 131 132@table @code 133 134@cindex @code{2byte} directive, ARC 135@item .2byte @var{expressions} 136*TODO* 137 138@cindex @code{3byte} directive, ARC 139@item .3byte @var{expressions} 140*TODO* 141 142@cindex @code{4byte} directive, ARC 143@item .4byte @var{expressions} 144*TODO* 145 146@cindex @code{extAuxRegister} directive, ARC 147@item .extAuxRegister @var{name},@var{address},@var{mode} 148The ARCtangent A4 has extensible auxiliary register space. The 149auxiliary registers can be defined in the assembler source code by 150using this directive. The first parameter is the @var{name} of the 151new auxiallry register. The second parameter is the @var{address} of 152the register in the auxiliary register memory map for the variant of 153the ARC. The third parameter specifies the @var{mode} in which the 154register can be operated is and it can be one of: 155 156@table @code 157@item r (readonly) 158@item w (write only) 159@item r|w (read or write) 160@end table 161 162For example: 163 164@smallexample 165 .extAuxRegister mulhi,0x12,w 166@end smallexample 167 168This specifies an extension auxiliary register called @emph{mulhi} 169which is at address 0x12 in the memory space and which is only 170writable. 171 172@cindex @code{extCondCode} directive, ARC 173@item .extCondCode @var{suffix},@var{value} 174The condition codes on the ARCtangent A4 are extensible and can be 175specified by means of this assembler directive. They are specified 176by the suffix and the value for the condition code. They can be used to 177specify extra condition codes with any values. For example: 178 179@smallexample 180 .extCondCode is_busy,0x14 181 182 add.is_busy r1,r2,r3 183 bis_busy _main 184@end smallexample 185 186@cindex @code{extCoreRegister} directive, ARC 187@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} 188Specifies an extension core register @var{name} for the application. 189This allows a register @var{name} with a valid @var{regnum} between 0 190and 60, with the following as valid values for @var{mode} 191 192@table @samp 193@item @emph{r} (readonly) 194@item @emph{w} (write only) 195@item @emph{r|w} (read or write) 196@end table 197 198 199The other parameter gives a description of the register having a 200@var{shortcut} in the pipeline. The valid values are: 201 202@table @code 203@item can_shortcut 204@item cannot_shortcut 205@end table 206 207For example: 208 209@smallexample 210 .extCoreRegister mlo,57,r,can_shortcut 211@end smallexample 212 213This defines an extension core register mlo with the value 57 which 214can shortcut the pipeline. 215 216@cindex @code{extInstruction} directive, ARC 217@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass} 218The ARCtangent A4 allows the user to specify extension instructions. 219The extension instructions are not macros. The assembler creates 220encodings for use of these instructions according to the specification 221by the user. The parameters are: 222 223@itemize @bullet 224@item @var{name} 225Name of the extension instruction 226 227@item @var{opcode} 228Opcode to be used. (Bits 27:31 in the encoding). Valid values 2290x10-0x1f or 0x03 230 231@item @var{subopcode} 232Subopcode to be used. Valid values are from 0x09-0x3f. However the 233correct value also depends on @var{syntaxclass} 234 235@item @var{suffixclass} 236Determines the kinds of suffixes to be allowed. Valid values are 237@code{SUFFIX_NONE}, @code{SUFFIX_COND}, 238@code{SUFFIX_FLAG} which indicates the absence or presence of 239conditional suffixes and flag setting by the extension instruction. 240It is also possible to specify that an instruction sets the flags and 241is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}. 242 243@item @var{syntaxclass} 244Determines the syntax class for the instruction. It can have the 245following values: 246 247@table @code 248@item @code{SYNTAX_2OP}: 2492 Operand Instruction 250@item @code{SYNTAX_3OP}: 2513 Operand Instruction 252@end table 253 254In addition there could be modifiers for the syntax class as described 255below: 256 257@itemize @minus 258Syntax Class Modifiers are: 259 260@item @code{OP1_MUST_BE_IMM}: 261Modifies syntax class SYNTAX_3OP, specifying that the first operand 262of a three-operand instruction must be an immediate (i.e., the result 263is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with 264SYNTAX_3OP as given in the example below. This could usually be used 265to set the flags using specific instructions and not retain results. 266 267@item @code{OP1_IMM_IMPLIED}: 268Modifies syntax class SYNTAX_20P, it specifies that there is an 269implied immediate destination operand which does not appear in the 270syntax. For example, if the source code contains an instruction like: 271 272@smallexample 273inst r1,r2 274@end smallexample 275 276it really means that the first argument is an implied immediate (that 277is, the result is discarded). This is the same as though the source 278code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it 279with SYNTAX_20P. 280 281@end itemize 282@end itemize 283 284For example, defining 64-bit multiplier with immediate operands: 285 286@smallexample 287.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , 288 SYNTAX_3OP|OP1_MUST_BE_IMM 289@end smallexample 290 291The above specifies an extension instruction called mp64 which has 3 operands, 292sets the flags, can be used with a condition code, for which the 293first operand is an immediate. (Equivalent to discarding the result 294of the operation). 295 296@smallexample 297 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED 298@end smallexample 299 300This describes a 2 operand instruction with an implicit first 301immediate operand. The result of this operation would be discarded. 302 303@cindex @code{half} directive, ARC 304@item .half @var{expressions} 305*TODO* 306 307@cindex @code{long} directive, ARC 308@item .long @var{expressions} 309*TODO* 310 311@cindex @code{option} directive, ARC 312@item .option @var{arc|arc5|arc6|arc7|arc8} 313The @code{.option} directive must be followed by the desired core 314version. Again @code{arc} is an alias for 315@code{arc@value{ARC_CORE_DEFAULT}}. 316 317Note: the @code{.option} directive overrides the command line option 318@code{-marc}; a warning is emitted when the version is not consistent 319between the two - even for the implicit default core version 320(arc@value{ARC_CORE_DEFAULT}). 321 322@cindex @code{short} directive, ARC 323@item .short @var{expressions} 324*TODO* 325 326@cindex @code{word} directive, ARC 327@item .word @var{expressions} 328*TODO* 329 330@end table 331 332 333@node ARC Opcodes 334@section Opcodes 335 336@cindex ARC opcodes 337@cindex opcodes for ARC 338 339For information on the ARC instruction set, see @cite{ARC Programmers 340Reference Manual}, ARC International (www.arc.com) 341