1@c Copyright (C) 1991-2014 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@ifset GENERIC 5@page 6@node M68HC11-Dependent 7@chapter M68HC11 and M68HC12 Dependent Features 8@end ifset 9@ifclear GENERIC 10@node Machine Dependencies 11@chapter M68HC11 and M68HC12 Dependent Features 12@end ifclear 13 14@cindex M68HC11 and M68HC12 support 15@menu 16* M68HC11-Opts:: M68HC11 and M68HC12 Options 17* M68HC11-Syntax:: Syntax 18* M68HC11-Modifiers:: Symbolic Operand Modifiers 19* M68HC11-Directives:: Assembler Directives 20* M68HC11-Float:: Floating Point 21* M68HC11-opcodes:: Opcodes 22@end menu 23 24@node M68HC11-Opts 25@section M68HC11 and M68HC12 Options 26 27@cindex options, M68HC11 28@cindex M68HC11 options 29The Motorola 68HC11 and 68HC12 version of @code{@value{AS}} have a few machine 30dependent options. 31 32@table @code 33 34@cindex @samp{-m68hc11} 35@item -m68hc11 36This option switches the assembler into the M68HC11 mode. In this mode, 37the assembler only accepts 68HC11 operands and mnemonics. It produces 38code for the 68HC11. 39 40@cindex @samp{-m68hc12} 41@item -m68hc12 42This option switches the assembler into the M68HC12 mode. In this mode, 43the assembler also accepts 68HC12 operands and mnemonics. It produces 44code for the 68HC12. A few 68HC11 instructions are replaced by 45some 68HC12 instructions as recommended by Motorola specifications. 46 47@cindex @samp{-m68hcs12} 48@item -m68hcs12 49This option switches the assembler into the M68HCS12 mode. This mode is 50similar to @samp{-m68hc12} but specifies to assemble for the 68HCS12 51series. The only difference is on the assembling of the @samp{movb} 52and @samp{movw} instruction when a PC-relative operand is used. 53 54@cindex @samp{-mm9s12x} 55@item -mm9s12x 56This option switches the assembler into the M9S12X mode. This mode is 57similar to @samp{-m68hc12} but specifies to assemble for the S12X 58series which is a superset of the HCS12. 59 60@cindex @samp{-mm9s12xg} 61@item -mm9s12xg 62This option switches the assembler into the XGATE mode for the RISC 63co-processor featured on some S12X-family chips. 64 65@cindex @samp{--xgate-ramoffset} 66@item --xgate-ramoffset 67This option instructs the linker to offset RAM addresses from S12X address 68space into XGATE address space. 69 70@cindex @samp{-mshort} 71@item -mshort 72This option controls the ABI and indicates to use a 16-bit integer ABI. 73It has no effect on the assembled instructions. 74This is the default. 75 76@cindex @samp{-mlong} 77@item -mlong 78This option controls the ABI and indicates to use a 32-bit integer ABI. 79 80@cindex @samp{-mshort-double} 81@item -mshort-double 82This option controls the ABI and indicates to use a 32-bit float ABI. 83This is the default. 84 85@cindex @samp{-mlong-double} 86@item -mlong-double 87This option controls the ABI and indicates to use a 64-bit float ABI. 88 89@cindex @samp{--strict-direct-mode} 90@item --strict-direct-mode 91You can use the @samp{--strict-direct-mode} option to disable 92the automatic translation of direct page mode addressing into 93extended mode when the instruction does not support direct mode. 94For example, the @samp{clr} instruction does not support direct page 95mode addressing. When it is used with the direct page mode, 96@code{@value{AS}} will ignore it and generate an absolute addressing. 97This option prevents @code{@value{AS}} from doing this, and the wrong 98usage of the direct page mode will raise an error. 99 100@cindex @samp{--short-branches} 101@item --short-branches 102The @samp{--short-branches} option turns off the translation of 103relative branches into absolute branches when the branch offset is 104out of range. By default @code{@value{AS}} transforms the relative 105branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne}, 106@samp{ble}, @samp{blt}, @samp{bhi}, @samp{bcc}, @samp{bls}, 107@samp{bcs}, @samp{bmi}, @samp{bvs}, @samp{bvs}, @samp{bra}) into 108an absolute branch when the offset is out of the -128 .. 127 range. 109In that case, the @samp{bsr} instruction is translated into a 110@samp{jsr}, the @samp{bra} instruction is translated into a 111@samp{jmp} and the conditional branches instructions are inverted and 112followed by a @samp{jmp}. This option disables these translations 113and @code{@value{AS}} will generate an error if a relative branch 114is out of range. This option does not affect the optimization 115associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes. 116 117@cindex @samp{--force-long-branches} 118@item --force-long-branches 119The @samp{--force-long-branches} option forces the translation of 120relative branches into absolute branches. This option does not affect 121the optimization associated to the @samp{jbra}, @samp{jbsr} and 122@samp{jbXX} pseudo opcodes. 123 124@cindex @samp{--print-insn-syntax} 125@item --print-insn-syntax 126You can use the @samp{--print-insn-syntax} option to obtain the 127syntax description of the instruction when an error is detected. 128 129@cindex @samp{--print-opcodes} 130@item --print-opcodes 131The @samp{--print-opcodes} option prints the list of all the 132instructions with their syntax. The first item of each line 133represents the instruction name and the rest of the line indicates 134the possible operands for that instruction. The list is printed 135in alphabetical order. Once the list is printed @code{@value{AS}} 136exits. 137 138@cindex @samp{--generate-example} 139@item --generate-example 140The @samp{--generate-example} option is similar to @samp{--print-opcodes} 141but it generates an example for each instruction instead. 142@end table 143 144@node M68HC11-Syntax 145@section Syntax 146 147@cindex M68HC11 syntax 148@cindex syntax, M68HC11 149 150In the M68HC11 syntax, the instruction name comes first and it may 151be followed by one or several operands (up to three). Operands are 152separated by comma (@samp{,}). In the normal mode, 153@code{@value{AS}} will complain if too many operands are specified for 154a given instruction. In the MRI mode (turned on with @samp{-M} option), 155it will treat them as comments. Example: 156 157@smallexample 158inx 159lda #23 160bset 2,x #4 161brclr *bot #8 foo 162@end smallexample 163 164@cindex line comment character, M68HC11 165@cindex M68HC11 line comment character 166The presence of a @samp{;} character or a @samp{!} character anywhere 167on a line indicates the start of a comment that extends to the end of 168that line. 169 170A @samp{*} or a @samp{#} character at the start of a line also 171introduces a line comment, but these characters do not work elsewhere 172on the line. If the first character of the line is a @samp{#} then as 173well as starting a comment, the line could also be logical line number 174directive (@pxref{Comments}) or a preprocessor control command 175(@pxref{Preprocessing}). 176 177@cindex line separator, M68HC11 178@cindex statement separator, M68HC11 179@cindex M68HC11 line separator 180The M68HC11 assembler does not currently support a line separator 181character. 182 183@cindex M68HC11 addressing modes 184@cindex addressing modes, M68HC11 185The following addressing modes are understood for 68HC11 and 68HC12: 186@table @dfn 187@item Immediate 188@samp{#@var{number}} 189 190@item Address Register 191@samp{@var{number},X}, @samp{@var{number},Y} 192 193The @var{number} may be omitted in which case 0 is assumed. 194 195@item Direct Addressing mode 196@samp{*@var{symbol}}, or @samp{*@var{digits}} 197 198@item Absolute 199@samp{@var{symbol}}, or @samp{@var{digits}} 200@end table 201 202The M68HC12 has other more complex addressing modes. All of them 203are supported and they are represented below: 204 205@table @dfn 206@item Constant Offset Indexed Addressing Mode 207@samp{@var{number},@var{reg}} 208 209The @var{number} may be omitted in which case 0 is assumed. 210The register can be either @samp{X}, @samp{Y}, @samp{SP} or 211@samp{PC}. The assembler will use the smaller post-byte definition 212according to the constant value (5-bit constant offset, 9-bit constant 213offset or 16-bit constant offset). If the constant is not known by 214the assembler it will use the 16-bit constant offset post-byte and the value 215will be resolved at link time. 216 217@item Offset Indexed Indirect 218@samp{[@var{number},@var{reg}]} 219 220The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}. 221 222@item Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement 223@samp{@var{number},-@var{reg}} 224@samp{@var{number},+@var{reg}} 225@samp{@var{number},@var{reg}-} 226@samp{@var{number},@var{reg}+} 227 228The number must be in the range @samp{-8}..@samp{+8} and must not be 0. 229The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}. 230 231@item Accumulator Offset 232@samp{@var{acc},@var{reg}} 233 234The accumulator register can be either @samp{A}, @samp{B} or @samp{D}. 235The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}. 236 237@item Accumulator D offset indexed-indirect 238@samp{[D,@var{reg}]} 239 240The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}. 241 242@end table 243 244For example: 245 246@smallexample 247ldab 1024,sp 248ldd [10,x] 249orab 3,+x 250stab -2,y- 251ldx a,pc 252sty [d,sp] 253@end smallexample 254 255 256@node M68HC11-Modifiers 257@section Symbolic Operand Modifiers 258 259@cindex M68HC11 modifiers 260@cindex syntax, M68HC11 261 262The assembler supports several modifiers when using symbol addresses 263in 68HC11 and 68HC12 instruction operands. The general syntax is 264the following: 265 266@smallexample 267%modifier(symbol) 268@end smallexample 269 270@table @code 271@cindex symbol modifiers 272@item %addr 273This modifier indicates to the assembler and linker to use 274the 16-bit physical address corresponding to the symbol. This is intended 275to be used on memory window systems to map a symbol in the memory bank window. 276If the symbol is in a memory expansion part, the physical address 277corresponds to the symbol address within the memory bank window. 278If the symbol is not in a memory expansion part, this is the symbol address 279(using or not using the %addr modifier has no effect in that case). 280 281@item %page 282This modifier indicates to use the memory page number corresponding 283to the symbol. If the symbol is in a memory expansion part, its page 284number is computed by the linker as a number used to map the page containing 285the symbol in the memory bank window. If the symbol is not in a memory 286expansion part, the page number is 0. 287 288@item %hi 289This modifier indicates to use the 8-bit high part of the physical 290address of the symbol. 291 292@item %lo 293This modifier indicates to use the 8-bit low part of the physical 294address of the symbol. 295 296@end table 297 298For example a 68HC12 call to a function @samp{foo_example} stored in memory 299expansion part could be written as follows: 300 301@smallexample 302call %addr(foo_example),%page(foo_example) 303@end smallexample 304 305and this is equivalent to 306 307@smallexample 308call foo_example 309@end smallexample 310 311And for 68HC11 it could be written as follows: 312 313@smallexample 314ldab #%page(foo_example) 315stab _page_switch 316jsr %addr(foo_example) 317@end smallexample 318 319@node M68HC11-Directives 320@section Assembler Directives 321 322@cindex assembler directives, M68HC11 323@cindex assembler directives, M68HC12 324@cindex M68HC11 assembler directives 325@cindex M68HC12 assembler directives 326 327The 68HC11 and 68HC12 version of @code{@value{AS}} have the following 328specific assembler directives: 329 330@table @code 331@item .relax 332@cindex assembler directive .relax, M68HC11 333@cindex M68HC11 assembler directive .relax 334The relax directive is used by the @samp{GNU Compiler} to emit a specific 335relocation to mark a group of instructions for linker relaxation. 336The sequence of instructions within the group must be known to the linker 337so that relaxation can be performed. 338 339@item .mode [mshort|mlong|mshort-double|mlong-double] 340@cindex assembler directive .mode, M68HC11 341@cindex M68HC11 assembler directive .mode 342This directive specifies the ABI. It overrides the @samp{-mshort}, 343@samp{-mlong}, @samp{-mshort-double} and @samp{-mlong-double} options. 344 345@item .far @var{symbol} 346@cindex assembler directive .far, M68HC11 347@cindex M68HC11 assembler directive .far 348This directive marks the symbol as a @samp{far} symbol meaning that it 349uses a @samp{call/rtc} calling convention as opposed to @samp{jsr/rts}. 350During a final link, the linker will identify references to the @samp{far} 351symbol and will verify the proper calling convention. 352 353@item .interrupt @var{symbol} 354@cindex assembler directive .interrupt, M68HC11 355@cindex M68HC11 assembler directive .interrupt 356This directive marks the symbol as an interrupt entry point. 357This information is then used by the debugger to correctly unwind the 358frame across interrupts. 359 360@item .xrefb @var{symbol} 361@cindex assembler directive .xrefb, M68HC11 362@cindex M68HC11 assembler directive .xrefb 363This directive is defined for compatibility with the 364@samp{Specification for Motorola 8 and 16-Bit Assembly Language Input 365Standard} and is ignored. 366 367@end table 368 369@node M68HC11-Float 370@section Floating Point 371 372@cindex floating point, M68HC11 373@cindex M68HC11 floating point 374Packed decimal (P) format floating literals are not supported. 375Feel free to add the code! 376 377The floating point formats generated by directives are these. 378 379@table @code 380@cindex @code{float} directive, M68HC11 381@item .float 382@code{Single} precision floating point constants. 383 384@cindex @code{double} directive, M68HC11 385@item .double 386@code{Double} precision floating point constants. 387 388@cindex @code{extend} directive M68HC11 389@cindex @code{ldouble} directive M68HC11 390@item .extend 391@itemx .ldouble 392@code{Extended} precision (@code{long double}) floating point constants. 393@end table 394 395@need 2000 396@node M68HC11-opcodes 397@section Opcodes 398 399@cindex M68HC11 opcodes 400@cindex opcodes, M68HC11 401@cindex instruction set, M68HC11 402 403@menu 404* M68HC11-Branch:: Branch Improvement 405@end menu 406 407@node M68HC11-Branch 408@subsection Branch Improvement 409 410@cindex pseudo-opcodes, M68HC11 411@cindex M68HC11 pseudo-opcodes 412@cindex branch improvement, M68HC11 413@cindex M68HC11 branch improvement 414 415Certain pseudo opcodes are permitted for branch instructions. 416They expand to the shortest branch instruction that reach the 417target. Generally these mnemonics are made by prepending @samp{j} to 418the start of Motorola mnemonic. These pseudo opcodes are not affected 419by the @samp{--short-branches} or @samp{--force-long-branches} options. 420 421The following table summarizes the pseudo-operations. 422 423@smallexample 424 Displacement Width 425 +-------------------------------------------------------------+ 426 | Options | 427 | --short-branches --force-long-branches | 428 +--------------------------+----------------------------------+ 429 Op |BYTE WORD | BYTE WORD | 430 +--------------------------+----------------------------------+ 431 bsr | bsr <pc-rel> <error> | jsr <abs> | 432 bra | bra <pc-rel> <error> | jmp <abs> | 433jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 434jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 435 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 436jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 437 | jmp <abs> | | 438 +--------------------------+----------------------------------+ 439XX: condition 440NX: negative of condition XX 441 442@end smallexample 443 444@table @code 445@item jbsr 446@itemx jbra 447These are the simplest jump pseudo-operations; they always map to one 448particular machine instruction, depending on the displacement to the 449branch target. 450 451@item jb@var{XX} 452Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations, 453where @var{XX} is a conditional branch or condition-code test. The full 454list of pseudo-ops in this family is: 455@smallexample 456 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 457 jbcs jbne jblt jble jbls jbvc jbmi 458@end smallexample 459 460For the cases of non-PC relative displacements and long displacements, 461@code{@value{AS}} issues a longer code fragment in terms of 462@var{NX}, the opposite condition to @var{XX}. For example, for the 463non-PC relative case: 464@smallexample 465 jb@var{XX} foo 466@end smallexample 467gives 468@smallexample 469 b@var{NX}s oof 470 jmp foo 471 oof: 472@end smallexample 473 474@end table 475 476 477