1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef __ANDROID__
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128
129 /*****************************************************************************/
130 /* */
131 /* Function Name : impeg2d_api_rel_display_frame */
132 /* */
133 /* Description : Release displ buffers that will be shared between decoder */
134 /* and application */
135 /* Inputs : Error message */
136 /* Globals : None */
137 /* Processing : Just prints error message to console */
138 /* Outputs : Error mesage to the console */
139 /* Returns : None */
140 /* */
141 /* Issues : <List any issues or problems with this function> */
142 /* */
143 /* Revision History: */
144 /* */
145 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
146 /* 27 05 2006 Sankar Creation */
147 /* */
148 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)149 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
150 void *pv_api_ip,
151 void *pv_api_op)
152 {
153
154 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
155 ivd_rel_display_frame_op_t *dec_rel_disp_op;
156
157 dec_state_t *ps_dec_state;
158 dec_state_multi_core_t *ps_dec_state_multi_core;
159
160
161 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
162 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
163
164 dec_rel_disp_op->u4_error_code = 0;
165 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
166 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
167
168
169 /* If not in shared disp buf mode, return */
170 if(0 == ps_dec_state->u4_share_disp_buf)
171 return IV_SUCCESS;
172
173 if(NULL == ps_dec_state->pv_pic_buf_mg)
174 return IV_SUCCESS;
175
176
177 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
178
179 return IV_SUCCESS;
180 }
181
182 /*****************************************************************************/
183 /* */
184 /* Function Name : impeg2d_api_set_display_frame */
185 /* */
186 /* Description : Sets display buffers that will be shared between decoder */
187 /* and application */
188 /* Inputs : Error message */
189 /* Globals : None */
190 /* Processing : Just prints error message to console */
191 /* Outputs : Error mesage to the console */
192 /* Returns : None */
193 /* */
194 /* Issues : <List any issues or problems with this function> */
195 /* */
196 /* Revision History: */
197 /* */
198 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
199 /* 27 05 2006 Sankar Creation */
200 /* */
201 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)202 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
203 void *pv_api_ip,
204 void *pv_api_op)
205 {
206
207 ivd_set_display_frame_ip_t *dec_disp_ip;
208 ivd_set_display_frame_op_t *dec_disp_op;
209
210 UWORD32 i;
211 dec_state_t *ps_dec_state;
212 dec_state_multi_core_t *ps_dec_state_multi_core;
213 UWORD32 u4_num_disp_bufs;
214
215
216 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
217 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
218 dec_disp_op->u4_error_code = 0;
219
220 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
221 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
222 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
223
224 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
225 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
226
227 if(ps_dec_state->u4_share_disp_buf)
228 {
229 pic_buf_t *ps_pic_buf;
230 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
231 for(i = 0; i < u4_num_disp_bufs; i++)
232 {
233
234 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
235 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
236 {
237 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
238 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
239 }
240 else
241 {
242 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
243 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
244 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
245 }
246
247 ps_pic_buf->i4_buf_id = i;
248
249 ps_pic_buf->u1_used_as_ref = 0;
250
251 ps_pic_buf->u4_ts = 0;
252
253 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
254 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
255 ps_pic_buf++;
256
257 }
258 }
259 memcpy(&(ps_dec_state->as_disp_buffers[0]),
260 &(dec_disp_ip->s_disp_buffer),
261 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
262
263 return IV_SUCCESS;
264
265 }
266
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)267 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
268 void *pv_api_ip,
269 void *pv_api_op)
270 {
271 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
272 impeg2d_ctl_set_num_cores_op_t *ps_op;
273 dec_state_t *ps_dec_state;
274 dec_state_multi_core_t *ps_dec_state_multi_core;
275
276 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
277 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
278
279 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
280 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
281
282 if(ps_ip->u4_num_cores > 0)
283 {
284
285
286 WORD32 i;
287 for(i = 0; i < MAX_THREADS; i++)
288 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
289 }
290 else
291 {
292 ps_dec_state->i4_num_cores = 1;
293 }
294 ps_op->u4_error_code = IV_SUCCESS;
295
296 return IV_SUCCESS;
297 }
298
299 /**
300 *******************************************************************************
301 *
302 * @brief
303 * Sets Processor type
304 *
305 * @par Description:
306 * Sets Processor type
307 *
308 * @param[in] ps_codec_obj
309 * Pointer to codec object at API level
310 *
311 * @param[in] pv_api_ip
312 * Pointer to input argument structure
313 *
314 * @param[out] pv_api_op
315 * Pointer to output argument structure
316 *
317 * @returns Status
318 *
319 * @remarks
320 *
321 *
322 *******************************************************************************
323 */
324
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)325 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
326 void *pv_api_ip,
327 void *pv_api_op)
328 {
329 impeg2d_ctl_set_processor_ip_t *ps_ip;
330 impeg2d_ctl_set_processor_op_t *ps_op;
331 dec_state_t *ps_codec;
332 dec_state_multi_core_t *ps_dec_state_multi_core;
333
334 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
335 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
336
337 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
338 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
339
340 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
341 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
342
343 impeg2d_init_function_ptr(ps_codec);
344
345
346 ps_op->u4_error_code = 0;
347 return IV_SUCCESS;
348 }
349 /*****************************************************************************/
350 /* */
351 /* Function Name : impeg2d_fill_mem_rec */
352 /* */
353 /* Description : */
354 /* Inputs : */
355 /* Globals : */
356 /* Processing : */
357 /* Outputs : */
358 /* Returns : */
359 /* */
360 /* Issues : */
361 /* */
362 /* Revision History: */
363 /* */
364 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
365 /* 17 09 2007 Rajendra C Y Draft */
366 /* */
367 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)368 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
369 impeg2d_fill_mem_rec_op_t *ps_op)
370 {
371 UWORD32 u4_i;
372
373 UWORD8 u1_no_rec = 0;
374 UWORD32 max_frm_width,max_frm_height,max_frm_size;
375 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
376 WORD32 i4_num_threads;
377 WORD32 i4_share_disp_buf, i4_chroma_format;
378 WORD32 i4_chroma_size;
379 UWORD32 u4_deinterlace;
380 UNUSED(u4_deinterlace);
381 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
382 max_frm_height = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht);
383
384 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
385
386 i4_chroma_size = max_frm_width * max_frm_height / 4;
387
388 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
389 {
390 #ifndef LOGO_EN
391 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
392 #else
393 i4_share_disp_buf = 0;
394 #endif
395 }
396 else
397 {
398 i4_share_disp_buf = 0;
399 }
400 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
401 {
402 i4_chroma_format = ps_ip->e_output_format;
403 }
404 else
405 {
406 i4_chroma_format = -1;
407 }
408
409 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
410 {
411 u4_deinterlace = ps_ip->u4_deinterlace;
412 }
413 else
414 {
415 u4_deinterlace = 0;
416 }
417
418
419 if( (i4_chroma_format != IV_YUV_420P) &&
420 (i4_chroma_format != IV_YUV_420SP_UV) &&
421 (i4_chroma_format != IV_YUV_420SP_VU))
422 {
423 i4_share_disp_buf = 0;
424 }
425
426 /* Disable deinterlacer in shared mode */
427 if(i4_share_disp_buf)
428 {
429 u4_deinterlace = 0;
430 }
431
432 /*************************************************************************/
433 /* Fill the memory requirement XDM Handle */
434 /*************************************************************************/
435 /* ! */
436 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
437 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
438 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
439
440 ps_mem_rec++;
441 u1_no_rec++;
442
443 {
444 /*************************************************************************/
445 /* Fill the memory requirement for threads context */
446 /*************************************************************************/
447 /* ! */
448 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
449 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
450 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
451
452 ps_mem_rec++;
453 u1_no_rec++;
454 }
455
456 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
457 {
458 /*************************************************************************/
459 /* Fill the memory requirement for MPEG2 Decoder Context */
460 /*************************************************************************/
461 /* ! */
462 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
463 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
464 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
465
466 ps_mem_rec++;
467 u1_no_rec++;
468
469 /* To store thread handle */
470 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
471 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
472 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
473
474 ps_mem_rec++;
475 u1_no_rec++;
476
477 /*************************************************************************/
478 /* Fill the memory requirement for Motion Compensation Buffers */
479 /*************************************************************************/
480 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
481 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
482
483 /* for mc_fw_buf.pu1_y */
484 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
485
486 /* for mc_fw_buf.pu1_u */
487 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
488
489 /* for mc_fw_buf.pu1_v */
490 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
491
492 /* for mc_bk_buf.pu1_y */
493 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
494
495 /* for mc_bk_buf.pu1_u */
496 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
497
498 /* for mc_bk_buf.pu1_v */
499 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
500
501 /* for mc_buf.pu1_y */
502 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
503
504 /* for mc_buf.pu1_u */
505 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
506
507 /* for mc_buf.pu1_v */
508 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
509
510 ps_mem_rec++;
511 u1_no_rec++;
512
513
514 /*************************************************************************/
515 /* Fill the memory requirement Stack Context */
516 /*************************************************************************/
517 /* ! */
518 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
519 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
520 ps_mem_rec->u4_mem_size = 392;
521
522 ps_mem_rec++;
523 u1_no_rec++;
524 }
525
526
527
528 {
529 /*************************************************************************/
530 /* Fill the memory requirement for Picture Buffer Manager */
531 /*************************************************************************/
532 /* ! */
533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
535 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
536
537 ps_mem_rec++;
538 u1_no_rec++;
539 }
540 /*************************************************************************/
541 /* Internal Frame Buffers */
542 /*************************************************************************/
543 /* ! */
544
545 {
546 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
547 {
548 /* ! */
549 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
550 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
551 if(0 == i4_share_disp_buf)
552 ps_mem_rec->u4_mem_size = max_frm_size;
553 else if(IV_YUV_420P != i4_chroma_format)
554 {
555 /* If color format is not 420P and it is shared, then allocate for chroma */
556 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
557 }
558 else
559 ps_mem_rec->u4_mem_size = 64;
560 ps_mem_rec++;
561 u1_no_rec++;
562 }
563 }
564
565
566
567 {
568 WORD32 i4_job_queue_size;
569 WORD32 i4_num_jobs;
570
571 /* One job per row of MBs */
572 i4_num_jobs = max_frm_height >> 4;
573
574 /* One format convert/frame copy job per row of MBs for non-shared mode*/
575 i4_num_jobs += max_frm_height >> 4;
576
577
578 i4_job_queue_size = impeg2_jobq_ctxt_size();
579 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
580 ps_mem_rec->u4_mem_size = i4_job_queue_size;
581 ps_mem_rec->u4_mem_alignment = 128;
582 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
583
584 ps_mem_rec++;
585 u1_no_rec++;
586
587 }
588
589 ps_mem_rec->u4_mem_alignment = 128;
590 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
591 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
592 ps_mem_rec++;
593 u1_no_rec++;
594
595 ps_mem_rec->u4_mem_alignment = 128;
596 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
597
598 if(IV_YUV_420P != i4_chroma_format)
599 ps_mem_rec->u4_mem_size = max_frm_size;
600 else
601 ps_mem_rec->u4_mem_size = 64;
602
603 ps_mem_rec++;
604 u1_no_rec++;
605
606 ps_mem_rec->u4_mem_alignment = 128;
607 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
608 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
609 ps_mem_rec++;
610 u1_no_rec++;
611 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
612 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
613 }
614
615
616 /*****************************************************************************/
617 /* */
618 /* Function Name : impeg2d_api_get_version */
619 /* */
620 /* Description : */
621 /* */
622 /* Inputs : */
623 /* Globals : <Does it use any global variables?> */
624 /* Outputs : */
625 /* Returns : void */
626 /* */
627 /* Issues : none */
628 /* */
629 /* Revision History: */
630 /* */
631 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
632 /* 22 10 2008 100356 Draft */
633 /* */
634 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)635 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
636 void *pv_api_ip,
637 void *pv_api_op)
638 {
639 char au1_version_string[512];
640
641 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
642 impeg2d_ctl_getversioninfo_op_t *ps_op;
643
644 UNUSED(ps_dechdl);
645
646 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
647 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
648
649 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
650
651 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
652 CODEC_VENDOR);
653
654 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
655 {
656 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
657 return (IV_FAIL);
658 }
659
660 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
661 >= (strlen(au1_version_string) + 1))
662 {
663 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
664 au1_version_string, (strlen(au1_version_string) + 1));
665 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
666 }
667 else
668 {
669 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
670 }
671
672 return (IV_SUCCESS);
673 }
674
675 /*****************************************************************************/
676 /* */
677 /* Function Name : impeg2d_api_get_buf_info */
678 /* */
679 /* Description : */
680 /* */
681 /* Inputs : */
682 /* Globals : <Does it use any global variables?> */
683 /* Outputs : */
684 /* Returns : void */
685 /* */
686 /* Issues : none */
687 /* */
688 /* Revision History: */
689 /* */
690 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
691 /* 22 10 2008 100356 Draft */
692 /* */
693 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)694 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
695 void *pv_api_ip,
696 void *pv_api_op)
697 {
698 dec_state_t *ps_dec_state;
699 dec_state_multi_core_t *ps_dec_state_multi_core;
700 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
701 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
702 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
703 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
704 UWORD32 u4_i, u4_stride, u4_height;
705 UNUSED(ps_ctl_bufinfo_ip);
706
707 ps_dec_state_multi_core =
708 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
709 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
710
711 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
712 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
713
714 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
715 {
716 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
717 MIN_OUT_BUFS_420;
718 }
719 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
720 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
721 {
722 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
723 MIN_OUT_BUFS_420SP;
724 }
725 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
726 {
727 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
728 MIN_OUT_BUFS_422ILE;
729 }
730 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
731 {
732 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
733 MIN_OUT_BUFS_RGB565;
734 }
735 else
736 {
737 //Invalid chroma format; Error code may be updated, verify in testing if needed
738 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
739 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
740 return IV_FAIL;
741 }
742
743 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
744 {
745 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
746 0;
747 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
748 0;
749 }
750
751 for(u4_i = 0;
752 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
753 u4_i++)
754 {
755 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
756 MAX_BITSTREAM_BUFFER_SIZE;
757 }
758
759 if (0 == ps_dec_state->u4_frm_buf_stride)
760 {
761 if (1 == ps_dec_state->u2_header_done)
762 {
763 u4_stride = ps_dec_state->u2_horizontal_size;
764 }
765 else
766 {
767 u4_stride = ps_dec_state->u2_create_max_width;
768 }
769 }
770 else
771 {
772 u4_stride = ps_dec_state->u4_frm_buf_stride;
773 }
774 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
775
776 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
777 {
778 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
779 (u4_stride * u4_height);
780 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
781 (u4_stride * u4_height) >> 2;
782 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
783 (u4_stride * u4_height) >> 2;
784 }
785 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
786 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
787 {
788 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
789 (u4_stride * u4_height);
790 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
791 (u4_stride * u4_height) >> 1;
792 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 0;
793 }
794 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
795 {
796 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
797 (u4_stride * u4_height) * 2;
798 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
799 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
800 0;
801 }
802
803 /* Adding initialization for 2 uninitialized values */
804 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
805 if(ps_dec_state->u4_share_disp_buf)
806 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
807 NUM_INT_FRAME_BUFFERS;
808 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
809
810 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
811
812 return (IV_SUCCESS);
813 }
814
815 /*****************************************************************************/
816 /* */
817 /* Function Name : impeg2d_api_set_flush_mode */
818 /* */
819 /* Description : */
820 /* */
821 /* Inputs : */
822 /* Globals : <Does it use any global variables?> */
823 /* Outputs : */
824 /* Returns : void */
825 /* */
826 /* Issues : none */
827 /* */
828 /* Revision History: */
829 /* */
830 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
831 /* 08 06 2009 100356 RAVI */
832 /* */
833 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)834 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
835 void *pv_api_ip,
836 void *pv_api_op)
837 {
838 dec_state_t *ps_dec_state;
839 dec_state_multi_core_t *ps_dec_state_multi_core;
840 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
841 (impeg2d_ctl_flush_op_t*)pv_api_op;
842
843 UNUSED(pv_api_ip);
844
845 ps_dec_state_multi_core =
846 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
847 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
848
849 ps_dec_state->u1_flushfrm = 1;
850
851 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
852 sizeof(impeg2d_ctl_flush_op_t);
853 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
854
855 return (IV_SUCCESS);
856 }
857
858 /*****************************************************************************/
859 /* */
860 /* Function Name : impeg2d_api_set_default */
861 /* */
862 /* Description : */
863 /* */
864 /* Inputs : */
865 /* Globals : <Does it use any global variables?> */
866 /* Outputs : */
867 /* Returns : void */
868 /* */
869 /* Issues : none */
870 /* */
871 /* Revision History: */
872 /* */
873 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
874 /* 08 06 2009 100356 RAVI */
875 /* */
876 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)877 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
878 void *pv_api_ip,
879 void *pv_api_op)
880 {
881 dec_state_t *ps_dec_state;
882 dec_state_multi_core_t *ps_dec_state_multi_core;
883 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
884 (impeg2d_ctl_set_config_op_t *)pv_api_op;
885
886 UNUSED(pv_api_ip);
887
888 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
889 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
890 sizeof(impeg2d_ctl_set_config_op_t);
891
892 ps_dec_state_multi_core =
893 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
894 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
895
896 ps_dec_state->u1_flushfrm = 0;
897 ps_dec_state->u2_decode_header = 1;
898
899 if (1 == ps_dec_state->u2_header_done)
900 {
901 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
902 }
903
904 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
905
906 return (IV_SUCCESS);
907
908 }
909
910 /*****************************************************************************/
911 /* */
912 /* Function Name : impeg2d_api_reset */
913 /* */
914 /* Description : */
915 /* */
916 /* Inputs : */
917 /* Globals : <Does it use any global variables?> */
918 /* Outputs : */
919 /* Returns : void */
920 /* */
921 /* Issues : none */
922 /* */
923 /* Revision History: */
924 /* */
925 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
926 /* 08 06 2009 100356 RAVI */
927 /* */
928 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)929 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
930 void *pv_api_ip,
931 void *pv_api_op)
932 {
933 dec_state_t *ps_dec_state;
934 dec_state_multi_core_t *ps_dec_state_multi_core;
935 UNUSED(pv_api_ip);
936 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
937
938 WORD32 i4_num_threads;
939
940 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
941 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
942
943 if(ps_dec_state_multi_core != NULL)
944 {
945 if(ps_dec_state->aps_ref_pics[1] != NULL)
946 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
947 if(ps_dec_state->aps_ref_pics[0] != NULL)
948 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
949 while(1)
950 {
951 pic_buf_t *ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
952 if(NULL == ps_disp_pic)
953 break;
954 if(0 == ps_dec_state->u4_share_disp_buf)
955 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
956
957 }
958
959 if((ps_dec_state->u4_deinterlace) && (NULL != ps_dec_state->ps_deint_pic))
960 {
961 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
962 ps_dec_state->ps_deint_pic->i4_buf_id,
963 MPEG2_BUF_MGR_DEINT);
964 }
965
966 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
967 {
968 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
969
970
971 /* --------------------------------------------------------------------- */
972 /* Initializations */
973
974 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
975 ps_dec_state->u4_frm_buf_stride = 0;
976 ps_dec_state->u2_is_mpeg2 = 0;
977 ps_dec_state->aps_ref_pics[0] = NULL;
978 ps_dec_state->aps_ref_pics[1] = NULL;
979 ps_dec_state->ps_deint_pic = NULL;
980 }
981 }
982 else
983 {
984 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
985 IMPEG2D_INIT_NOT_DONE;
986 }
987
988 return(IV_SUCCESS);
989 }
990
991 /*****************************************************************************/
992 /* */
993 /* Function Name : impeg2d_api_set_params */
994 /* */
995 /* Description : */
996 /* */
997 /* Inputs : */
998 /* Globals : <Does it use any global variables?> */
999 /* Outputs : */
1000 /* Returns : void */
1001 /* */
1002 /* Issues : none */
1003 /* */
1004 /* Revision History: */
1005 /* */
1006 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1007 /* 08 06 2009 100356 RAVI */
1008 /* */
1009 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1010 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1011 {
1012 dec_state_t *ps_dec_state;
1013 dec_state_multi_core_t *ps_dec_state_multi_core;
1014 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1015 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1016
1017 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1018 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1019
1020 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1021 {
1022 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1023 return(IV_FAIL);
1024 }
1025
1026 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1027 {
1028 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1029 return(IV_FAIL);
1030 }
1031
1032 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1033 {
1034 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1035 return(IV_FAIL);
1036 }
1037
1038 if(ps_dec_state->u2_header_done == 1)
1039 {
1040 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1041 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1042 {
1043 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1044 return(IV_FAIL);
1045 }
1046
1047 }
1048
1049
1050 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1051
1052 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1053 {
1054 if(ps_dec_state->u2_header_done == 1)
1055 {
1056 if (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd > ps_dec_state->u2_frame_width)
1057 {
1058 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1059 }
1060 }
1061 else
1062 {
1063 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1064 }
1065
1066 }
1067 else
1068 {
1069
1070 if(ps_dec_state->u2_header_done == 1)
1071 {
1072 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1073 }
1074 else
1075 {
1076 ps_dec_state->u4_frm_buf_stride = 0;
1077 }
1078 }
1079
1080
1081 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1082 {
1083 ps_dec_state->u1_flushfrm = 0;
1084 }
1085
1086
1087 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1088 return(IV_SUCCESS);
1089
1090 }
1091
1092 /*****************************************************************************/
1093 /* */
1094 /* Function Name : impeg2d_api_get_status */
1095 /* */
1096 /* Description : */
1097 /* */
1098 /* Inputs : */
1099 /* Globals : <Does it use any global variables?> */
1100 /* Outputs : */
1101 /* Returns : void */
1102 /* */
1103 /* Issues : none */
1104 /* */
1105 /* Revision History: */
1106 /* */
1107 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1108 /* 08 06 2009 100356 RAVI */
1109 /* */
1110 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1111 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1112 void *pv_api_ip,
1113 void *pv_api_op)
1114 {
1115 dec_state_t *ps_dec_state;
1116 dec_state_multi_core_t *ps_dec_state_multi_core;
1117 UWORD32 u4_i,u4_stride,u4_height;
1118 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1119 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1120 UNUSED(ps_ctl_dec_ip);
1121
1122 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1123 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1124
1125 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1126 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1127 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1128 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1129 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1130
1131
1132 if(ps_dec_state->u2_progressive_sequence == 1)
1133 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1134 else
1135 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1136
1137
1138 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1139 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1140 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1141
1142
1143 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1144 {
1145 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1146 }
1147 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1148 {
1149 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1150 }
1151 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1152 {
1153 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1154 }
1155 else
1156 {
1157 //Invalid chroma format; Error code may be updated, verify in testing if needed
1158 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1159 return IV_FAIL;
1160 }
1161
1162 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1163 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1164
1165 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1166 {
1167 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1168 }
1169
1170 u4_stride = ps_dec_state->u4_frm_buf_stride;
1171 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1172
1173 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1174 {
1175 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1176 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1177 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1178 }
1179 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1180 {
1181 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1182 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1183 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1184 }
1185 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1186 {
1187 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1188 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1189 }
1190
1191 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1192
1193 return(IV_SUCCESS);
1194
1195 }
1196
1197 /**
1198 *******************************************************************************
1199 *
1200 * @brief
1201 * Gets frame dimensions/offsets
1202 *
1203 * @par Description:
1204 * Gets frame buffer chararacteristics such a x & y offsets display and
1205 * buffer dimensions
1206 *
1207 * @param[in] ps_codec_obj
1208 * Pointer to codec object at API level
1209 *
1210 * @param[in] pv_api_ip
1211 * Pointer to input argument structure
1212 *
1213 * @param[out] pv_api_op
1214 * Pointer to output argument structure
1215 *
1216 * @returns Status
1217 *
1218 * @remarks
1219 *
1220 *
1221 *******************************************************************************
1222 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1223 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1224 void *pv_api_ip,
1225 void *pv_api_op)
1226 {
1227 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1228 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1229 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1230 dec_state_t *ps_codec;
1231 dec_state_multi_core_t *ps_dec_state_multi_core;
1232
1233 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1234 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1235
1236
1237 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1238 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1239 UNUSED(ps_ip);
1240 if(ps_codec->u2_header_done)
1241 {
1242 disp_wd = ps_codec->u2_horizontal_size;
1243 disp_ht = ps_codec->u2_vertical_size;
1244
1245 if(0 == ps_codec->u4_share_disp_buf)
1246 {
1247 buffer_wd = disp_wd;
1248 buffer_ht = disp_ht;
1249 }
1250 else
1251 {
1252 buffer_wd = ps_codec->u2_frame_width;
1253 buffer_ht = ps_codec->u2_frame_height;
1254 }
1255 }
1256 else
1257 {
1258
1259 disp_wd = ps_codec->u2_create_max_width;
1260 disp_ht = ps_codec->u2_create_max_height;
1261
1262 if(0 == ps_codec->u4_share_disp_buf)
1263 {
1264 buffer_wd = disp_wd;
1265 buffer_ht = disp_ht;
1266 }
1267 else
1268 {
1269 buffer_wd = ALIGN16(disp_wd);
1270 buffer_ht = ALIGN16(disp_ht);
1271
1272 }
1273 }
1274 if(ps_codec->u2_frame_width > buffer_wd)
1275 buffer_wd = ps_codec->u2_frame_width;
1276
1277 x_offset = 0;
1278 y_offset = 0;
1279
1280
1281 ps_op->u4_disp_wd[0] = disp_wd;
1282 ps_op->u4_disp_ht[0] = disp_ht;
1283 ps_op->u4_buffer_wd[0] = buffer_wd;
1284 ps_op->u4_buffer_ht[0] = buffer_ht;
1285 ps_op->u4_x_offset[0] = x_offset;
1286 ps_op->u4_y_offset[0] = y_offset;
1287
1288 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1289 >> 1);
1290 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1291 >> 1);
1292 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1293 >> 1);
1294 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1295 >> 1);
1296 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1297 >> 1);
1298 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1299 >> 1);
1300
1301 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1302 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1303 {
1304 ps_op->u4_disp_wd[2] = 0;
1305 ps_op->u4_disp_ht[2] = 0;
1306 ps_op->u4_buffer_wd[2] = 0;
1307 ps_op->u4_buffer_ht[2] = 0;
1308 ps_op->u4_x_offset[2] = 0;
1309 ps_op->u4_y_offset[2] = 0;
1310
1311 ps_op->u4_disp_wd[1] <<= 1;
1312 ps_op->u4_buffer_wd[1] <<= 1;
1313 ps_op->u4_x_offset[1] <<= 1;
1314 }
1315
1316 return IV_SUCCESS;
1317
1318 }
1319
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1320 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1321 {
1322 WORD32 i4_cmd;
1323 IV_API_CALL_STATUS_T u4_error_code;
1324 UWORD32 *pu4_api_ip;
1325
1326 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1327 if(IV_SUCCESS != u4_error_code)
1328 {
1329 return u4_error_code;
1330 }
1331
1332
1333 pu4_api_ip = (UWORD32 *)pv_api_ip;
1334 i4_cmd = *(pu4_api_ip + 1);
1335
1336 switch(i4_cmd)
1337 {
1338
1339 case IV_CMD_GET_NUM_MEM_REC:
1340 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1341 break;
1342
1343 case IV_CMD_FILL_NUM_MEM_REC:
1344 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1345 break;
1346
1347 case IV_CMD_INIT:
1348 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1349 break;
1350
1351 case IVD_CMD_SET_DISPLAY_FRAME:
1352 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1353 break;
1354
1355 case IVD_CMD_REL_DISPLAY_FRAME:
1356 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1357 break;
1358
1359 case IVD_CMD_VIDEO_DECODE:
1360 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1361 break;
1362
1363 case IV_CMD_RETRIEVE_MEMREC:
1364 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1365 break;
1366
1367 case IVD_CMD_VIDEO_CTL:
1368 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1369 break;
1370
1371 default:
1372 break;
1373 }
1374
1375 return(u4_error_code);
1376
1377 }
1378
1379 /*****************************************************************************/
1380 /* */
1381 /* Function Name : impeg2d_api_num_mem_rec */
1382 /* */
1383 /* Description : The function get the number mem records library needs */
1384 /* Inputs : Error message */
1385 /* Globals : None */
1386 /* Processing : Just prints error message to console */
1387 /* Outputs : Error mesage to the console */
1388 /* Returns : None */
1389 /* */
1390 /* Issues : <List any issues or problems with this function> */
1391 /* */
1392 /* Revision History: */
1393 /* */
1394 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1395 /* 23 09 2010 Hamsalekha Creation */
1396 /* */
1397 /*****************************************************************************/
1398
1399
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1400 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1401 {
1402 /* To Query No of Memory Records */
1403 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1404 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1405
1406 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1407 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1408
1409 UNUSED(ps_query_mem_rec_ip);
1410 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1411
1412 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1413
1414 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1415
1416
1417 return(IV_SUCCESS);
1418
1419 }
1420
1421
1422 /*****************************************************************************/
1423 /* */
1424 /* Function Name : impeg2d_api_fill_mem_rec */
1425 /* */
1426 /* Description : Thsi functions fills details of each mem record lib needs*/
1427 /* Inputs : Error message */
1428 /* Globals : None */
1429 /* Processing : Just prints error message to console */
1430 /* Outputs : Error mesage to the console */
1431 /* Returns : None */
1432 /* */
1433 /* Issues : <List any issues or problems with this function> */
1434 /* */
1435 /* Revision History: */
1436 /* */
1437 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1438 /* 23 09 2010 Hamsalekha Creation */
1439 /* */
1440 /*****************************************************************************/
1441
1442
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1443 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1444 {
1445
1446 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1447 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1448
1449
1450 ps_mem_q_ip = pv_api_ip;
1451 ps_mem_q_op = pv_api_op;
1452
1453
1454 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1455 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1456
1457
1458 return(IV_SUCCESS);
1459
1460 }
1461
1462
1463
1464 /*****************************************************************************/
1465 /* */
1466 /* Function Name : impeg2d_api_init */
1467 /* */
1468 /* Description : */
1469 /* Inputs : */
1470 /* Globals : */
1471 /* Processing : */
1472 /* Outputs : */
1473 /* Returns : */
1474 /* */
1475 /* Issues : */
1476 /* */
1477 /* Revision History: */
1478 /* */
1479 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1480 /* 17 09 2007 Rajendra C Y Draft */
1481 /* */
1482 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1483 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1484 void *ps_ip,
1485 void *ps_op)
1486 {
1487 UWORD32 i;
1488
1489 void *pv;
1490 UWORD32 u4_size;
1491
1492 dec_state_t *ps_dec_state;
1493 dec_state_multi_core_t *ps_dec_state_multi_core;
1494 UWORD32 u4_num_mem_rec;
1495 iv_mem_rec_t *ps_mem_rec ;
1496 iv_mem_rec_t *ps_frm_buf;
1497 iv_obj_t *ps_dec_handle;
1498 WORD32 i4_max_wd, i4_max_ht;
1499
1500 impeg2d_init_ip_t *ps_dec_init_ip;
1501 impeg2d_init_op_t *ps_dec_init_op;
1502 WORD32 i4_num_threads;
1503 UWORD32 u4_share_disp_buf, u4_chroma_format;
1504 UWORD32 u4_deinterlace;
1505
1506 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1507 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1508
1509 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1510 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1511
1512 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1513 {
1514 #ifndef LOGO_EN
1515 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1516 #else
1517 u4_share_disp_buf = 0;
1518 #endif
1519 }
1520 else
1521 {
1522 u4_share_disp_buf = 0;
1523 }
1524
1525 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1526
1527 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1528 {
1529 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1530 }
1531 else
1532 {
1533 u4_deinterlace = 0;
1534 }
1535
1536 if( (u4_chroma_format != IV_YUV_420P) &&
1537 (u4_chroma_format != IV_YUV_420SP_UV) &&
1538 (u4_chroma_format != IV_YUV_420SP_VU))
1539 {
1540 u4_share_disp_buf = 0;
1541 }
1542
1543 /* Disable deinterlacer in shared mode */
1544 if(u4_share_disp_buf)
1545 {
1546 u4_deinterlace = 0;
1547 }
1548
1549 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1550 ps_mem_rec ++;
1551
1552
1553 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1554
1555
1556 /* Except memTab[0], all other memTabs are initialized to zero */
1557 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1558 {
1559 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1560 ps_mem_rec++;
1561 }
1562
1563 /* Reinitializing memTab[0] memory base address */
1564 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1565
1566
1567 /* memTab[0] is for codec Handle,redundant currently not being used */
1568 ps_dec_handle = ps_mem_rec->pv_base;
1569 u4_num_mem_rec = 1;
1570 ps_mem_rec++;
1571
1572
1573
1574
1575
1576 /* decoder handle */
1577 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1578 u4_num_mem_rec++;
1579 ps_mem_rec++;
1580
1581
1582 {
1583 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1584
1585 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1586 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1587 }
1588
1589
1590 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1591 {
1592 /*************************************************************************/
1593 /* For MPEG2 Decoder Context */
1594 /*************************************************************************/
1595 ps_dec_state = ps_mem_rec->pv_base;
1596
1597 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1598
1599 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1600
1601 ps_dec_state->i4_num_cores = 1;
1602 /* @ */ /* Used for storing MemRecords */
1603 u4_num_mem_rec++;
1604 ps_mem_rec++;
1605
1606 /* Thread handle */
1607 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1608 u4_num_mem_rec++;
1609 ps_mem_rec++;
1610
1611 /*************************************************************************/
1612 /* For Motion Compensation Buffers */
1613 /*************************************************************************/
1614 pv = ps_mem_rec->pv_base;
1615
1616 /* for mc_fw_buf.pu1_y */
1617
1618 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1619 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1620
1621 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1622 /* for mc_fw_buf.pu1_u */
1623
1624 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1625 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1626
1627 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1628
1629 /* for mc_fw_buf.pu1_v */
1630
1631 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1632 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1633
1634 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1635
1636 /* for mc_bk_buf.pu1_y */
1637
1638 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1639 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1640
1641 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1642
1643 /* for mc_bk_buf.pu1_u */
1644
1645 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1646 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1647
1648 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1649
1650 /* for mc_bk_buf.pu1_v */
1651
1652 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1653 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1654
1655 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1656
1657 /* for mc_buf.pu1_y */
1658
1659 ps_dec_state->s_mc_buf.pu1_y = pv;
1660 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1661
1662 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1663
1664 /* for mc_buf.pu1_u */
1665
1666 ps_dec_state->s_mc_buf.pu1_u = pv;
1667 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1668
1669 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1670
1671 /* for mc_buf.pu1_v */
1672
1673 ps_dec_state->s_mc_buf.pu1_v = pv;
1674
1675 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1676
1677 u4_num_mem_rec++;
1678 ps_mem_rec++;
1679
1680
1681
1682 ps_dec_state->pv_pic_buf_mg = 0;
1683
1684 /*************************************************************************/
1685 /* For saving stack context to support global error handling */
1686 /*************************************************************************/
1687 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1688 u4_num_mem_rec++;
1689 ps_mem_rec++;
1690
1691 }
1692
1693
1694
1695
1696
1697 /*************************************************************************/
1698 /* For Picture Buffer Manager */
1699 /*************************************************************************/
1700 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1701
1702 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1703 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1704
1705 u4_num_mem_rec++;
1706 ps_mem_rec++;
1707
1708
1709
1710 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1711 {
1712
1713 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1714
1715
1716 /* --------------------------------------------------------------------- */
1717 /* Initializations */
1718
1719 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1720
1721
1722 {
1723 UWORD32 u4_max_frm_width,u4_max_frm_height;
1724
1725 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1726 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1727
1728 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1729 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1730
1731 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1732 ps_dec_state->u4_frm_buf_stride = 0 ;
1733 ps_dec_state->u2_frame_width = u4_max_frm_width;
1734 ps_dec_state->u2_picture_width = u4_max_frm_width;
1735 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1736
1737 ps_dec_state->u2_frame_height = u4_max_frm_height;
1738 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1739 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1740 ps_dec_state->u4_deinterlace = u4_deinterlace;
1741 ps_dec_state->ps_deint_pic = NULL;
1742 }
1743 }
1744
1745
1746 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1747
1748 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1749 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1750 {
1751 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1752 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1753 return(IV_FAIL);
1754
1755
1756 }
1757
1758 /* --------------------------------------------------------------------- */
1759
1760
1761 /* ! */
1762 // picture buffer manager initialization will be done only for first thread
1763 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1764 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1765
1766 /*************************************************************************/
1767 /* Internal Frame Buffers */
1768 /*************************************************************************/
1769
1770
1771 /* Set first frame to grey */
1772 {
1773 ps_frm_buf = ps_mem_rec;
1774 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1775 ps_frm_buf++;
1776 }
1777
1778 if(0 == ps_dec_state->u4_share_disp_buf)
1779 {
1780 pic_buf_t *ps_pic_buf;
1781 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1782 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1783 {
1784 UWORD8 *pu1_buf;
1785 pu1_buf = ps_mem_rec->pv_base;
1786
1787 ps_pic_buf->pu1_y = pu1_buf;
1788 pu1_buf += i4_max_ht * i4_max_wd;
1789
1790 ps_pic_buf->pu1_u = pu1_buf;
1791 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1792
1793 ps_pic_buf->pu1_v = pu1_buf;
1794 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1795
1796 ps_pic_buf->i4_buf_id = i;
1797
1798 ps_pic_buf->u1_used_as_ref = 0;
1799
1800 ps_pic_buf->u4_ts = 0;
1801
1802 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1803 ps_mem_rec++;
1804 ps_pic_buf++;
1805 }
1806 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1807 }
1808 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1809 {
1810 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1811 {
1812 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1813 ps_mem_rec++;
1814 }
1815
1816 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1817 }
1818 else
1819 {
1820 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
1821 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1822 }
1823
1824
1825 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1826
1827
1828 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
1829 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
1830 ps_mem_rec++;
1831
1832 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
1833 {
1834 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
1835 return(IV_FAIL);
1836
1837 }
1838
1839 ps_dec_state->u1_flushfrm = 0;
1840 ps_dec_state->u1_flushcnt = 0;
1841 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
1842
1843
1844 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
1845 ps_mem_rec++;
1846
1847 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
1848 ps_mem_rec++;
1849
1850
1851 /*************************************************************************/
1852 /* Last MemTab is used for storing TabRecords */
1853 /*************************************************************************/
1854 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
1855 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
1856 /* Updating in Decoder Context with memRecords */
1857 u4_num_mem_rec++;
1858 ps_mem_rec++;
1859 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
1860
1861
1862 ps_dec_state->u4_num_frames_decoded = 0;
1863 ps_dec_state->aps_ref_pics[0] = NULL;
1864 ps_dec_state->aps_ref_pics[1] = NULL;
1865
1866 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
1867
1868 impeg2d_init_arch(ps_dec_state);
1869
1870 impeg2d_init_function_ptr(ps_dec_state);
1871
1872 return(IV_SUCCESS);
1873 }
1874
1875 /*****************************************************************************/
1876 /* */
1877 /* Function Name : impeg2d_api_retrieve_mem_rec */
1878 /* */
1879 /* Description : */
1880 /* */
1881 /* Inputs : */
1882 /* Globals : <Does it use any global variables?> */
1883 /* Outputs : */
1884 /* Returns : void */
1885 /* */
1886 /* Issues : none */
1887 /* */
1888 /* Revision History: */
1889 /* */
1890 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1891 /* 22 10 2008 100356 Draft */
1892 /* */
1893 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1894 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
1895 void *pv_api_ip,
1896 void *pv_api_op)
1897 {
1898 UWORD32 u4_i;
1899 dec_state_t *ps_dec_state;
1900 dec_state_multi_core_t *ps_dec_state_multi_core;
1901 iv_mem_rec_t *ps_mem_rec;
1902 iv_mem_rec_t *ps_temp_rec;
1903
1904
1905
1906 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
1907 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
1908
1909 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
1910 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
1911
1912 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
1913 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1914 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1915 ps_temp_rec = ps_dec_state->pv_memTab;
1916
1917 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
1918 {
1919 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
1920 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
1921 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
1922 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
1923 }
1924
1925 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1926 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
1927
1928 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
1929 IMPEG2D_PRINT_STATISTICS();
1930
1931
1932 return(IV_SUCCESS);
1933
1934 }
1935
1936 /*****************************************************************************/
1937 /* */
1938 /* Function Name : impeg2d_api_ctl */
1939 /* */
1940 /* Description : */
1941 /* */
1942 /* Inputs : */
1943 /* Globals : <Does it use any global variables?> */
1944 /* Outputs : */
1945 /* Returns : void */
1946 /* */
1947 /* Issues : none */
1948 /* */
1949 /* Revision History: */
1950 /* */
1951 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1952 /* 22 10 2008 100356 Draft */
1953 /* */
1954 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1955 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
1956 void *pv_api_ip,
1957 void *pv_api_op)
1958 {
1959 WORD32 i4_sub_cmd;
1960 UWORD32 *pu4_api_ip;
1961 IV_API_CALL_STATUS_T u4_error_code;
1962
1963 pu4_api_ip = (UWORD32 *)pv_api_ip;
1964 i4_sub_cmd = *(pu4_api_ip + 2);
1965
1966 switch(i4_sub_cmd)
1967 {
1968 case IVD_CMD_CTL_GETPARAMS:
1969 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
1970 (void *)pv_api_op);
1971 break;
1972
1973 case IVD_CMD_CTL_SETPARAMS:
1974 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
1975 (void *)pv_api_op);
1976 break;
1977
1978 case IVD_CMD_CTL_RESET:
1979 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
1980 (void *)pv_api_op);
1981 break;
1982
1983 case IVD_CMD_CTL_SETDEFAULT:
1984 u4_error_code = impeg2d_api_set_default(ps_dechdl,
1985 (void *)pv_api_ip,
1986 (void *)pv_api_op);
1987 break;
1988
1989 case IVD_CMD_CTL_FLUSH:
1990 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
1991 (void *)pv_api_ip,
1992 (void *)pv_api_op);
1993 break;
1994
1995 case IVD_CMD_CTL_GETBUFINFO:
1996 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
1997 (void *)pv_api_ip,
1998 (void *)pv_api_op);
1999 break;
2000
2001 case IVD_CMD_CTL_GETVERSION:
2002 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2003 (void *)pv_api_op);
2004 break;
2005
2006 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2007 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2008 (void *)pv_api_ip,
2009 (void *)pv_api_op);
2010 break;
2011
2012 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2013 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2014 (void *)pv_api_ip,
2015 (void *)pv_api_op);
2016 break;
2017
2018 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2019 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2020 (void *)pv_api_op);
2021 break;
2022
2023 default:
2024 u4_error_code = IV_FAIL;
2025 break;
2026 }
2027
2028 return (u4_error_code);
2029
2030 }
2031
2032 /*****************************************************************************/
2033 /* */
2034 /* Function Name : impeg2d_api_check_struct_sanity */
2035 /* */
2036 /* Description : */
2037 /* */
2038 /* Inputs : */
2039 /* Globals : <Does it use any global variables?> */
2040 /* Outputs : */
2041 /* Returns : void */
2042 /* */
2043 /* Issues : none */
2044 /* */
2045 /* Revision History: */
2046 /* */
2047 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2048 /* 22 10 2008 100356 Draft */
2049 /* */
2050 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2051 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2052 void *pv_api_ip,
2053 void *pv_api_op)
2054 {
2055 WORD32 i4_cmd;
2056 UWORD32 *pu4_api_ip;
2057 UWORD32 *pu4_api_op;
2058 WORD32 i,j;
2059
2060 if(NULL == pv_api_op)
2061 return(IV_FAIL);
2062
2063 if(NULL == pv_api_ip)
2064 return(IV_FAIL);
2065
2066 pu4_api_ip = (UWORD32 *)pv_api_ip;
2067 pu4_api_op = (UWORD32 *)pv_api_op;
2068 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2069
2070 /* error checks on handle */
2071 switch(i4_cmd)
2072 {
2073 case IV_CMD_GET_NUM_MEM_REC:
2074 case IV_CMD_FILL_NUM_MEM_REC:
2075 break;
2076 case IV_CMD_INIT:
2077 if(ps_handle == NULL)
2078 {
2079 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2080 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2081 return IV_FAIL;
2082 }
2083
2084 if(ps_handle->u4_size != sizeof(iv_obj_t))
2085 {
2086 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2087 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2088 return IV_FAIL;
2089 }
2090 break;
2091 case IVD_CMD_GET_DISPLAY_FRAME:
2092 case IVD_CMD_VIDEO_DECODE:
2093 case IV_CMD_RETRIEVE_MEMREC:
2094 case IVD_CMD_SET_DISPLAY_FRAME:
2095 case IVD_CMD_REL_DISPLAY_FRAME:
2096 case IVD_CMD_VIDEO_CTL:
2097 {
2098 if(ps_handle == NULL)
2099 {
2100 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2101 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2102 return IV_FAIL;
2103 }
2104
2105 if(ps_handle->u4_size != sizeof(iv_obj_t))
2106 {
2107 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2108 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2109 return IV_FAIL;
2110 }
2111 if(ps_handle->pv_fxns != impeg2d_api_function)
2112 {
2113 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2114 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2115 return IV_FAIL;
2116 }
2117
2118 if(ps_handle->pv_codec_handle == NULL)
2119 {
2120 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2121 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2122 return IV_FAIL;
2123 }
2124 }
2125 break;
2126 default:
2127 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2128 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2129 return IV_FAIL;
2130 }
2131
2132 switch(i4_cmd)
2133 {
2134 case IV_CMD_GET_NUM_MEM_REC:
2135 {
2136 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2137 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2138 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2139
2140 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2141 {
2142 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2143 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2144 return(IV_FAIL);
2145 }
2146
2147 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2148 {
2149 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2150 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2151 return(IV_FAIL);
2152 }
2153 }
2154 break;
2155 case IV_CMD_FILL_NUM_MEM_REC:
2156 {
2157 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2158 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2159 iv_mem_rec_t *ps_mem_rec;
2160
2161 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2162
2163 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2164 {
2165 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2166 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2167 return(IV_FAIL);
2168 }
2169
2170 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2171 {
2172 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2173 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2174 return(IV_FAIL);
2175 }
2176
2177 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2178 {
2179 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2180 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2181 return(IV_FAIL);
2182 }
2183
2184 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2185 {
2186 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2187 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2188 return(IV_FAIL);
2189 }
2190
2191 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2192 {
2193 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2194 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2195 return(IV_FAIL);
2196 }
2197
2198 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2199 {
2200 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2201 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2202 return(IV_FAIL);
2203 }
2204
2205 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2206 {
2207 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2208 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2209 return(IV_FAIL);
2210 }
2211
2212 /* check memrecords sizes are correct */
2213 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2214 for(i=0;i<NUM_MEM_RECORDS;i++)
2215 {
2216 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2217 {
2218 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2219 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2220 return IV_FAIL;
2221 }
2222 }
2223 }
2224 break;
2225
2226 case IV_CMD_INIT:
2227 {
2228 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2229 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2230 iv_mem_rec_t *ps_mem_rec;
2231 UWORD32 u4_tot_num_mem_recs;
2232
2233 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2234
2235 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2236 {
2237 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2238 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2239 return(IV_FAIL);
2240 }
2241
2242 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2243 {
2244 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2245 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2246 return(IV_FAIL);
2247 }
2248
2249 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2250
2251
2252
2253
2254 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2255 {
2256 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2257 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2258 return(IV_FAIL);
2259 }
2260
2261 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2262 {
2263 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2264 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2265 return(IV_FAIL);
2266 }
2267
2268 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2269 {
2270 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2271 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2272 return(IV_FAIL);
2273 }
2274
2275 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2276 {
2277 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2278 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2279 return(IV_FAIL);
2280 }
2281
2282 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2283 {
2284 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2285 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2286 return(IV_FAIL);
2287 }
2288
2289 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2290 {
2291 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2292 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2293 return(IV_FAIL);
2294 }
2295
2296 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2297 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2298 {
2299 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2300 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2301 return(IV_FAIL);
2302 }
2303
2304 /* verify number of mem records */
2305 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2306 {
2307 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2308 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2309 return IV_FAIL;
2310 }
2311
2312 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2313 /* verify wether first memrecord is handle or not */
2314 /*
2315 if(ps_mem_rec->pv_base != ps_handle)
2316 {
2317 // indicate the incorrect handle error
2318 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2319 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2320 return IV_FAIL;
2321 }
2322 */
2323 /* check memrecords sizes are correct */
2324 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2325 {
2326 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2327 {
2328 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2329 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2330 return IV_FAIL;
2331 }
2332 }
2333
2334 /* verify memtabs for overlapping regions */
2335 {
2336 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2337 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2338
2339
2340 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2341 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2342 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2343 {
2344 /* This array is populated to check memtab overlapp */
2345 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2346 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2347
2348 for(j = 0; j < i; j++)
2349 {
2350 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2351 {
2352 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2353 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2354 return IV_FAIL;
2355 }
2356
2357 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2358 {
2359 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2360 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2361 return IV_FAIL;
2362 }
2363
2364 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2365 {
2366 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2367 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2368 return IV_FAIL;
2369 }
2370 }
2371 }
2372 }
2373
2374
2375
2376
2377 {
2378 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2379
2380 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2381 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2382 IV_API_CALL_STATUS_T e_status;
2383 WORD32 i4_num_memrec;
2384 {
2385
2386 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2387 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2388
2389
2390 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2391 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2392
2393 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2394 impeg2d_api_function(NULL,
2395 (void *)&s_no_of_mem_rec_query_ip,
2396 (void *)&s_no_of_mem_rec_query_op);
2397
2398 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2399
2400
2401
2402 }
2403
2404
2405 /* initialize mem records array with sizes */
2406 for(i = 0; i < i4_num_memrec; i++)
2407 {
2408 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2409 }
2410
2411 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2412 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2413 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2414 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2415 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2416 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2417 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2418 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2419
2420
2421 e_status = impeg2d_api_function(NULL,
2422 (void *)&s_fill_mem_rec_ip,
2423 (void *)&s_fill_mem_rec_op);
2424 if(IV_FAIL == e_status)
2425 {
2426 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2427 return(IV_FAIL);
2428 }
2429
2430
2431
2432 for(i = 0; i < i4_num_memrec; i ++)
2433 {
2434 if(ps_mem_rec[i].pv_base == NULL)
2435 {
2436 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2437 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2438 return IV_FAIL;
2439 }
2440 #ifdef CHECK_ALIGN
2441
2442 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2443 {
2444 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2445 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2446 return IV_FAIL;
2447 }
2448 #endif //CHECK_ALIGN
2449 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2450 {
2451 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2452 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2453 return IV_FAIL;
2454 }
2455
2456 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2457 {
2458 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2459 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2460 return IV_FAIL;
2461 }
2462
2463 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2464 {
2465 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2466 {
2467 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2468 {
2469 continue;
2470 }
2471 }
2472 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2473 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2474 return IV_FAIL;
2475 }
2476 }
2477 }
2478
2479
2480 }
2481 break;
2482
2483 case IVD_CMD_GET_DISPLAY_FRAME:
2484 {
2485 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2486 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2487
2488 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2489
2490 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2491 {
2492 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2493 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2494 return(IV_FAIL);
2495 }
2496
2497 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2498 {
2499 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2500 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2501 return(IV_FAIL);
2502 }
2503
2504 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2505 {
2506 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2507 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2508 return IV_FAIL;
2509 }
2510
2511 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2512 {
2513 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2514 {
2515 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2516 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2517 return IV_FAIL;
2518 }
2519
2520 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2521 {
2522 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2523 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2524 return IV_FAIL;
2525 }
2526 /*
2527 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2528 {
2529 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2530 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2531 return IV_FAIL;
2532 }
2533 */
2534 }
2535 }
2536 break;
2537 case IVD_CMD_REL_DISPLAY_FRAME:
2538 {
2539 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2540 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2541
2542 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2543
2544 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2545 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2546 {
2547 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2548 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2549 return(IV_FAIL);
2550 }
2551
2552 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2553 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2554 {
2555 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2556 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2557 return(IV_FAIL);
2558 }
2559
2560 }
2561 break;
2562
2563
2564 case IVD_CMD_SET_DISPLAY_FRAME:
2565 {
2566 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2567 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2568 UWORD32 j, i;
2569
2570 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2571
2572 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2573 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2574 {
2575 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2576 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2577 return(IV_FAIL);
2578 }
2579
2580 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2581 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2582 {
2583 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2584 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2585 return(IV_FAIL);
2586 }
2587
2588 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2589 {
2590 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2591 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2592 return IV_FAIL;
2593 }
2594
2595 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2596 {
2597 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2598 {
2599 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2600 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2601 return IV_FAIL;
2602 }
2603
2604 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2605 {
2606 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2607 {
2608 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2609 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2610 return IV_FAIL;
2611 }
2612
2613 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2614 {
2615 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2616 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2617 return IV_FAIL;
2618 }
2619 }
2620 }
2621 }
2622 break;
2623
2624 case IVD_CMD_VIDEO_DECODE:
2625 {
2626 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2627 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2628
2629 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2630
2631 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2632 {
2633 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2634 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2635 return(IV_FAIL);
2636 }
2637
2638 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2639 {
2640 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2641 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2642 return(IV_FAIL);
2643 }
2644
2645 }
2646 break;
2647
2648 case IV_CMD_RETRIEVE_MEMREC:
2649 {
2650 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2651 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2652 iv_mem_rec_t *ps_mem_rec;
2653
2654 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2655
2656 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2657 {
2658 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2659 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2660 return(IV_FAIL);
2661 }
2662
2663 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2664 {
2665 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2666 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2667 return(IV_FAIL);
2668 }
2669
2670 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2671 /* check memrecords sizes are correct */
2672 for(i=0;i < NUM_MEM_RECORDS ; i++)
2673 {
2674 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2675 {
2676 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2677 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2678 return IV_FAIL;
2679 }
2680 }
2681 }
2682 break;
2683
2684 case IVD_CMD_VIDEO_CTL:
2685 {
2686 UWORD32 *pu4_ptr_cmd;
2687 UWORD32 u4_sub_command;
2688
2689 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2690 pu4_ptr_cmd += 2;
2691 u4_sub_command = *pu4_ptr_cmd;
2692
2693 switch(u4_sub_command)
2694 {
2695 case IVD_CMD_CTL_SETPARAMS:
2696 {
2697 impeg2d_ctl_set_config_ip_t *ps_ip;
2698 impeg2d_ctl_set_config_op_t *ps_op;
2699 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2700 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2701
2702 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2703
2704 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2705 {
2706 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2707 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2708 return IV_FAIL;
2709 }
2710 }
2711 case IVD_CMD_CTL_SETDEFAULT:
2712 {
2713 impeg2d_ctl_set_config_op_t *ps_op;
2714 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2715 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2716
2717 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2718 {
2719 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2720 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2721 return IV_FAIL;
2722 }
2723 }
2724 break;
2725
2726 case IVD_CMD_CTL_GETPARAMS:
2727 {
2728 impeg2d_ctl_getstatus_ip_t *ps_ip;
2729 impeg2d_ctl_getstatus_op_t *ps_op;
2730
2731 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2732 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2733
2734 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2735
2736 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2737 {
2738 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2739 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2740 return IV_FAIL;
2741 }
2742 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2743 {
2744 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2745 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2746 return IV_FAIL;
2747 }
2748 }
2749 break;
2750
2751 case IVD_CMD_CTL_GETBUFINFO:
2752 {
2753 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2754 impeg2d_ctl_getbufinfo_op_t *ps_op;
2755 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2756 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2757
2758 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2759
2760 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2761 {
2762 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2763 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2764 return IV_FAIL;
2765 }
2766 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
2767 {
2768 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2769 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2770 return IV_FAIL;
2771 }
2772 }
2773 break;
2774
2775 case IVD_CMD_CTL_GETVERSION:
2776 {
2777 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
2778 impeg2d_ctl_getversioninfo_op_t *ps_op;
2779 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
2780 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
2781
2782 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
2783
2784 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
2785 {
2786 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2787 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2788 return IV_FAIL;
2789 }
2790 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
2791 {
2792 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2793 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2794 return IV_FAIL;
2795 }
2796 }
2797 break;
2798
2799 case IVD_CMD_CTL_FLUSH:
2800 {
2801 impeg2d_ctl_flush_ip_t *ps_ip;
2802 impeg2d_ctl_flush_op_t *ps_op;
2803 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
2804 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
2805
2806 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
2807
2808 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
2809 {
2810 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2811 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2812 return IV_FAIL;
2813 }
2814 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
2815 {
2816 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2817 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2818 return IV_FAIL;
2819 }
2820 }
2821 break;
2822
2823 case IVD_CMD_CTL_RESET:
2824 {
2825 impeg2d_ctl_reset_ip_t *ps_ip;
2826 impeg2d_ctl_reset_op_t *ps_op;
2827 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
2828 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
2829
2830 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
2831
2832 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
2833 {
2834 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2835 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2836 return IV_FAIL;
2837 }
2838 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
2839 {
2840 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2841 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2842 return IV_FAIL;
2843 }
2844 }
2845 break;
2846
2847 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2848 {
2849 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
2850 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
2851
2852 ps_ip =
2853 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
2854 ps_op =
2855 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
2856
2857 if(ps_ip->u4_size
2858 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
2859 {
2860 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2861 ps_op->u4_error_code |=
2862 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2863 return IV_FAIL;
2864 }
2865
2866 if(ps_op->u4_size
2867 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
2868 {
2869 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2870 ps_op->u4_error_code |=
2871 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2872 return IV_FAIL;
2873 }
2874
2875 break;
2876 }
2877
2878 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2879 {
2880 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
2881 impeg2d_ctl_set_num_cores_op_t *ps_op;
2882
2883 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
2884 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
2885
2886 if(ps_ip->u4_size
2887 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
2888 {
2889 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2890 ps_op->u4_error_code |=
2891 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2892 return IV_FAIL;
2893 }
2894
2895 if(ps_op->u4_size
2896 != sizeof(impeg2d_ctl_set_num_cores_op_t))
2897 {
2898 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2899 ps_op->u4_error_code |=
2900 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2901 return IV_FAIL;
2902 }
2903
2904 #ifdef MULTICORE
2905 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
2906 #else
2907 if(ps_ip->u4_num_cores != 1)
2908 #endif
2909 {
2910 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2911 return IV_FAIL;
2912 }
2913 break;
2914 }
2915 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2916 {
2917 impeg2d_ctl_set_processor_ip_t *ps_ip;
2918 impeg2d_ctl_set_processor_op_t *ps_op;
2919
2920 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
2921 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
2922
2923 if(ps_ip->u4_size
2924 != sizeof(impeg2d_ctl_set_processor_ip_t))
2925 {
2926 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2927 ps_op->u4_error_code |=
2928 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2929 return IV_FAIL;
2930 }
2931
2932 if(ps_op->u4_size
2933 != sizeof(impeg2d_ctl_set_processor_op_t))
2934 {
2935 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2936 ps_op->u4_error_code |=
2937 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2938 return IV_FAIL;
2939 }
2940
2941 break;
2942 }
2943 default:
2944 break;
2945
2946 }
2947 }
2948 break;
2949
2950 default:
2951 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2952 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
2953 return IV_FAIL;
2954 }
2955
2956
2957 }
2958
2959 return IV_SUCCESS;
2960 }
2961
2962 /*****************************************************************************/
2963 /* */
2964 /* Function Name : impeg2d_api_entity */
2965 /* */
2966 /* Description : */
2967 /* */
2968 /* Inputs : */
2969 /* Globals : <Does it use any global variables?> */
2970 /* Outputs : */
2971 /* Returns : void */
2972 /* */
2973 /* Issues : none */
2974 /* */
2975 /* Revision History: */
2976 /* */
2977 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2978 /* 22 10 2008 100356 Draft */
2979 /* */
2980 /*****************************************************************************/
2981
2982
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2983 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
2984 void *pv_api_ip,
2985 void *pv_api_op)
2986 {
2987 iv_obj_t *ps_dec_handle;
2988 dec_state_t *ps_dec_state;
2989 dec_state_multi_core_t *ps_dec_state_multi_core;
2990
2991 impeg2d_video_decode_ip_t *ps_dec_ip;
2992
2993 impeg2d_video_decode_op_t *ps_dec_op;
2994 WORD32 bytes_remaining;
2995 pic_buf_t *ps_disp_pic;
2996
2997
2998
2999 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3000 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3001
3002 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3003
3004 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3005 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3006 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3007
3008 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3009
3010 if(ps_dechdl == NULL)
3011 {
3012 return(IV_FAIL);
3013 }
3014
3015
3016
3017 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3018 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3019
3020 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3021 if(0 == ps_dec_state->u4_share_disp_buf)
3022 {
3023 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3024 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3025 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3026 }
3027
3028 ps_dec_state->ps_disp_pic = NULL;
3029 ps_dec_state->i4_frame_decoded = 0;
3030 /*rest bytes consumed */
3031 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3032
3033 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3034
3035 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3036 {
3037 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3038 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3039 return IV_FAIL;
3040 }
3041
3042
3043 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3044 {
3045 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3046 return(IV_FAIL);
3047 }
3048
3049 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3050 {
3051 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3052 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3053 }
3054
3055 if((1 != ps_dec_state->u2_decode_header) && ((bytes_remaining > 0) || ps_dec_state->u1_flushfrm))
3056 {
3057 if(ps_dec_state->u1_flushfrm)
3058 {
3059 if(ps_dec_state->aps_ref_pics[1] != NULL)
3060 {
3061 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3062 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3063 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3064
3065 ps_dec_state->aps_ref_pics[1] = NULL;
3066 ps_dec_state->aps_ref_pics[0] = NULL;
3067
3068 }
3069 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3070 {
3071 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3072 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3073
3074 ps_dec_state->aps_ref_pics[0] = NULL;
3075 }
3076 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3077 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3078
3079 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3080
3081 ps_dec_state->ps_disp_pic = ps_disp_pic;
3082 if(ps_disp_pic == NULL)
3083 {
3084 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3085 }
3086 else
3087 {
3088 WORD32 fmt_conv;
3089 if(0 == ps_dec_state->u4_share_disp_buf)
3090 {
3091 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3092 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3093 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3094 fmt_conv = 1;
3095 }
3096 else
3097 {
3098 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3099 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3100 {
3101 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3102 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3103 fmt_conv = 0;
3104 }
3105 else
3106 {
3107 UWORD8 *pu1_buf;
3108
3109 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3110 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3111
3112 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3113 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3114 fmt_conv = 1;
3115 }
3116 }
3117
3118 if(fmt_conv == 1)
3119 {
3120 iv_yuv_buf_t *ps_dst;
3121
3122
3123 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3124 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3125 {
3126 impeg2d_deinterlace(ps_dec_state,
3127 ps_disp_pic,
3128 ps_dst,
3129 0,
3130 ps_dec_state->u2_vertical_size);
3131
3132 }
3133 else
3134 {
3135 impeg2d_format_convert(ps_dec_state,
3136 ps_disp_pic,
3137 ps_dst,
3138 0,
3139 ps_dec_state->u2_vertical_size);
3140 }
3141 }
3142
3143 if(ps_dec_state->u4_deinterlace)
3144 {
3145 if(ps_dec_state->ps_deint_pic)
3146 {
3147 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3148 ps_dec_state->ps_deint_pic->i4_buf_id,
3149 MPEG2_BUF_MGR_DEINT);
3150 }
3151 ps_dec_state->ps_deint_pic = ps_disp_pic;
3152 }
3153 if(0 == ps_dec_state->u4_share_disp_buf)
3154 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3155
3156 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3157 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3158 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3159
3160 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3161 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3162
3163 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3164
3165 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3166
3167 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3168
3169 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3170 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3171 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3172
3173 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3174 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3175 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3176
3177 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3178 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3179 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3180 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3181
3182 switch(ps_dec_state->i4_chromaFormat)
3183 {
3184 case IV_YUV_420SP_UV:
3185 case IV_YUV_420SP_VU:
3186 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3187 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3188 break;
3189 case IV_YUV_422ILE:
3190 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3191 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3192 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3193 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3194 break;
3195 default:
3196 break;
3197 }
3198
3199
3200 }
3201 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3202 {
3203 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3204 {
3205 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3206 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3207 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3208 ps_dec_state->u4_frm_buf_stride,
3209 ps_dec_state->u2_horizontal_size,
3210 ps_dec_state->u2_vertical_size,
3211 ps_dec_state->i4_chromaFormat,
3212 ps_dec_state->u2_horizontal_size,
3213 ps_dec_state->u2_vertical_size);
3214 }
3215 return(IV_SUCCESS);
3216 }
3217 else
3218 {
3219 ps_dec_state->u1_flushfrm = 0;
3220
3221 return(IV_FAIL);
3222 }
3223
3224 }
3225 else if(ps_dec_state->u1_flushfrm==0)
3226 {
3227 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3228 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3229 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3230 {
3231 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3232 return(IV_FAIL);
3233 }
3234
3235 if(1 == ps_dec_state->u4_share_disp_buf)
3236 {
3237 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3238 {
3239 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3240 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3241 return IV_FAIL;
3242 }
3243 }
3244
3245
3246 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3247
3248 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3249
3250 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3251
3252 if (0 == ps_dec_state->u4_frm_buf_stride)
3253 {
3254 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3255 }
3256
3257 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3258 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3259 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3260
3261 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3262 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3263 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3264
3265 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3266 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3267 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3268 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3269
3270 switch(ps_dec_state->i4_chromaFormat)
3271 {
3272 case IV_YUV_420SP_UV:
3273 case IV_YUV_420SP_VU:
3274 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3275 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3276 break;
3277 case IV_YUV_422ILE:
3278 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3279 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3280 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3281 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3282 break;
3283 default:
3284 break;
3285 }
3286
3287 if( ps_dec_state->u1_flushfrm == 0)
3288 {
3289 ps_dec_state->u1_flushcnt = 0;
3290
3291 /*************************************************************************/
3292 /* Frame Decode */
3293 /*************************************************************************/
3294
3295 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3296
3297 if (IVD_ERROR_NONE ==
3298 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3299 {
3300 if(ps_dec_state->u1_first_frame_done == 0)
3301 {
3302 ps_dec_state->u1_first_frame_done = 1;
3303 }
3304
3305 if(ps_dec_state->ps_disp_pic)
3306 {
3307 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3308 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3309 {
3310 case I_PIC :
3311 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3312 break;
3313
3314 case P_PIC:
3315 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3316 break;
3317
3318 case B_PIC:
3319 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3320 break;
3321
3322 case D_PIC:
3323 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3324 break;
3325
3326 default :
3327 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3328 break;
3329 }
3330 }
3331 else
3332 {
3333 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3334 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3335 }
3336
3337 ps_dec_state->u4_num_frames_decoded++;
3338 }
3339 }
3340 else
3341 {
3342 ps_dec_state->u1_flushcnt++;
3343 }
3344 }
3345 if(ps_dec_state->ps_disp_pic)
3346 {
3347 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3348 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3349
3350 if(0 == ps_dec_state->u4_share_disp_buf)
3351 {
3352 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3353 }
3354 }
3355
3356 if(ps_dec_state->u4_deinterlace)
3357 {
3358 if(ps_dec_state->ps_deint_pic)
3359 {
3360 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3361 ps_dec_state->ps_deint_pic->i4_buf_id,
3362 MPEG2_BUF_MGR_DEINT);
3363 }
3364 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3365 }
3366
3367 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3368 {
3369 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3370 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3371 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3372 ps_dec_state->u4_frm_buf_stride,
3373 ps_dec_state->u2_horizontal_size,
3374 ps_dec_state->u2_vertical_size,
3375 ps_dec_state->i4_chromaFormat,
3376 ps_dec_state->u2_horizontal_size,
3377 ps_dec_state->u2_vertical_size);
3378 }
3379
3380 }
3381
3382 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3383 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3384
3385
3386 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3387 return IV_FAIL;
3388 else
3389 return IV_SUCCESS;
3390 }
3391