1@c Copyright (C) 2005-2014 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@c man end 5 6@ifset GENERIC 7@page 8@node Blackfin-Dependent 9@chapter Blackfin Dependent Features 10@end ifset 11 12@ifclear GENERIC 13@node Machine Dependencies 14@chapter Blackfin Dependent Features 15@end ifclear 16 17@cindex Blackfin support 18@menu 19* Blackfin Options:: Blackfin Options 20* Blackfin Syntax:: Blackfin Syntax 21* Blackfin Directives:: Blackfin Directives 22@end menu 23 24@node Blackfin Options 25@section Options 26@cindex Blackfin options (none) 27@cindex options for Blackfin (none) 28 29@c man begin OPTIONS 30@table @gcctabopt 31 32@cindex @code{-mcpu=} command line option, Blackfin 33@item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]} 34This option specifies the target processor. The optional @var{sirevision} 35is not used in assembler. It's here such that GCC can easily pass down its 36@code{-mcpu=} option. The assembler will issue an 37error message if an attempt is made to assemble an instruction which 38will not execute on the target processor. The following processor names are 39recognized: 40@code{bf504}, 41@code{bf506}, 42@code{bf512}, 43@code{bf514}, 44@code{bf516}, 45@code{bf518}, 46@code{bf522}, 47@code{bf523}, 48@code{bf524}, 49@code{bf525}, 50@code{bf526}, 51@code{bf527}, 52@code{bf531}, 53@code{bf532}, 54@code{bf533}, 55@code{bf534}, 56@code{bf535} (not implemented yet), 57@code{bf536}, 58@code{bf537}, 59@code{bf538}, 60@code{bf539}, 61@code{bf542}, 62@code{bf542m}, 63@code{bf544}, 64@code{bf544m}, 65@code{bf547}, 66@code{bf547m}, 67@code{bf548}, 68@code{bf548m}, 69@code{bf549}, 70@code{bf549m}, 71@code{bf561}, 72and 73@code{bf592}. 74 75@cindex @code{-mfdpic} command line option, Blackfin 76@item -mfdpic 77Assemble for the FDPIC ABI. 78 79@cindex @code{-mno-fdpic} command line option, Blackfin 80@cindex @code{-mnopic} command line option, Blackfin 81@item -mno-fdpic 82@itemx -mnopic 83Disable -mfdpic. 84@end table 85@c man end 86 87@node Blackfin Syntax 88@section Syntax 89@cindex Blackfin syntax 90@cindex syntax, Blackfin 91 92@table @code 93@item Special Characters 94Assembler input is free format and may appear anywhere on the line. 95One instruction may extend across multiple lines or more than one 96instruction may appear on the same line. White space (space, tab, 97comments or newline) may appear anywhere between tokens. A token must 98not have embedded spaces. Tokens include numbers, register names, 99keywords, user identifiers, and also some multicharacter special 100symbols like "+=", "/*" or "||". 101 102Comments are introduced by the @samp{#} character and extend to the 103end of the current line. If the @samp{#} appears as the first 104character of a line, the whole line is treated as a comment, but in 105this case the line can also be a logical line number directive 106(@pxref{Comments}) or a preprocessor control command 107(@pxref{Preprocessing}). 108 109@item Instruction Delimiting 110A semicolon must terminate every instruction. Sometimes a complete 111instruction will consist of more than one operation. There are two 112cases where this occurs. The first is when two general operations 113are combined. Normally a comma separates the different parts, as in 114 115@smallexample 116a0= r3.h * r2.l, a1 = r3.l * r2.h ; 117@end smallexample 118 119The second case occurs when a general instruction is combined with one 120or two memory references for joint issue. The latter portions are 121set off by a "||" token. 122 123@smallexample 124a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 125@end smallexample 126 127Multiple instructions can occur on the same line. Each must be 128terminated by a semicolon character. 129 130@item Register Names 131 132The assembler treats register names and instruction keywords in a case 133insensitive manner. User identifiers are case sensitive. Thus, R3.l, 134R3.L, r3.l and r3.L are all equivalent input to the assembler. 135 136Register names are reserved and may not be used as program identifiers. 137 138Some operations (such as "Move Register") require a register pair. 139Register pairs are always data registers and are denoted using a colon, 140eg., R3:2. The larger number must be written firsts. Note that the 141hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. 142 143Some instructions (such as --SP (Push Multiple)) require a group of 144adjacent registers. Adjacent registers are denoted in the syntax by 145the range enclosed in parentheses and separated by a colon, eg., (R7:3). 146Again, the larger number appears first. 147 148Portions of a particular register may be individually specified. This 149is written with a dot (".") following the register name and then a 150letter denoting the desired portion. For 32-bit registers, ".H" 151denotes the most significant ("High") portion. ".L" denotes the 152least-significant portion. The subdivisions of the 40-bit registers 153are described later. 154 155@item Accumulators 156The set of 40-bit registers A1 and A0 that normally contain data that 157is being manipulated. Each accumulator can be accessed in four ways. 158 159@table @code 160@item one 40-bit register 161The register will be referred to as A1 or A0. 162@item one 32-bit register 163The registers are designated as A1.W or A0.W. 164@item two 16-bit registers 165The registers are designated as A1.H, A1.L, A0.H or A0.L. 166@item one 8-bit register 167The registers are designated as A1.X or A0.X for the bits that 168extend beyond bit 31. 169@end table 170 171@item Data Registers 172The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that 173normally contain data for manipulation. These are abbreviated as 174D-register or Dreg. Data registers can be accessed as 32-bit registers 175or as two independent 16-bit registers. The least significant 16 bits 176of each register is called the "low" half and is designated with ".L" 177following the register name. The most significant 16 bits are called 178the "high" half and is designated with ".H" following the name. 179 180@smallexample 181 R7.L, r2.h, r4.L, R0.H 182@end smallexample 183 184@item Pointer Registers 185The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that 186normally contain byte addresses of data structures. These are 187abbreviated as P-register or Preg. 188 189@smallexample 190p2, p5, fp, sp 191@end smallexample 192 193@item Stack Pointer SP 194The stack pointer contains the 32-bit address of the last occupied 195byte location in the stack. The stack grows by decrementing the 196stack pointer. 197 198@item Frame Pointer FP 199The frame pointer contains the 32-bit address of the previous frame 200pointer in the stack. It is located at the top of a frame. 201 202@item Loop Top 203LT0 and LT1. These registers contain the 32-bit address of the top of 204a zero overhead loop. 205 206@item Loop Count 207LC0 and LC1. These registers contain the 32-bit counter of the zero 208overhead loop executions. 209 210@item Loop Bottom 211LB0 and LB1. These registers contain the 32-bit address of the bottom 212of a zero overhead loop. 213 214@item Index Registers 215The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte 216addresses of data structures. Abbreviated I-register or Ireg. 217 218@item Modify Registers 219The set of 32-bit registers (M0, M1, M2, M3) that normally contain 220offset values that are added and subtracted to one of the index 221registers. Abbreviated as Mreg. 222 223@item Length Registers 224The set of 32-bit registers (L0, L1, L2, L3) that normally contain the 225length in bytes of the circular buffer. Abbreviated as Lreg. Clear 226the Lreg to disable circular addressing for the corresponding Ireg. 227 228@item Base Registers 229The set of 32-bit registers (B0, B1, B2, B3) that normally contain the 230base address in bytes of the circular buffer. Abbreviated as Breg. 231 232@item Floating Point 233The Blackfin family has no hardware floating point but the .float 234directive generates ieee floating point numbers for use with software 235floating point libraries. 236 237@item Blackfin Opcodes 238For detailed information on the Blackfin machine instruction set, see 239the Blackfin(r) Processor Instruction Set Reference. 240 241@end table 242 243@node Blackfin Directives 244@section Directives 245@cindex Blackfin directives 246@cindex directives, Blackfin 247 248The following directives are provided for compatibility with the VDSP assembler. 249 250@table @code 251@item .byte2 252Initializes a two byte data object. 253 254This maps to the @code{.short} directive. 255@item .byte4 256Initializes a four byte data object. 257 258This maps to the @code{.int} directive. 259@item .db 260Initializes a single byte data object. 261 262This directive is a synonym for @code{.byte}. 263@item .dw 264Initializes a two byte data object. 265 266This directive is a synonym for @code{.byte2}. 267@item .dd 268Initializes a four byte data object. 269 270This directive is a synonym for @code{.byte4}. 271@item .var 272Define and initialize a 32 bit data object. 273@end table 274