1 /* tc-v850.c -- Assembler code for the NEC V850
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "subsegs.h"
24 #include "opcode/v850.h"
25 #include "dwarf2dbg.h"
26
27 /* Sign-extend a 16-bit number. */
28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
29
30 /* Set to TRUE if we want to be pedantic about signed overflows. */
31 static bfd_boolean warn_signed_overflows = FALSE;
32 static bfd_boolean warn_unsigned_overflows = FALSE;
33
34 /* Indicates the target BFD machine number. */
35 static int machine = -1;
36
37
38 /* Indiciates the target BFD architecture. */
39 int v850_target_arch = bfd_arch_v850_rh850;
40 const char * v850_target_format = "elf32-v850-rh850";
41 static flagword v850_e_flags = 0;
42
43 /* Indicates the target processor(s) for the assemble. */
44 static int processor_mask = 0;
45
46 /* Structure to hold information about predefined registers. */
47 struct reg_name
48 {
49 const char *name;
50 int value;
51 unsigned int processors;
52 };
53
54 /* Generic assembler global variables which must be defined by all
55 targets. */
56
57 /* Characters which always start a comment. */
58 const char comment_chars[] = "#";
59
60 /* Characters which start a comment at the beginning of a line. */
61 const char line_comment_chars[] = ";#";
62
63 /* Characters which may be used to separate multiple commands on a
64 single line. */
65 const char line_separator_chars[] = ";";
66
67 /* Characters which are used to indicate an exponent in a floating
68 point number. */
69 const char EXP_CHARS[] = "eE";
70
71 /* Characters which mean that a number is a floating point constant,
72 as in 0d1.0. */
73 const char FLT_CHARS[] = "dD";
74
75 const relax_typeS md_relax_table[] =
76 {
77 /* Conditional branches.(V850/V850E, max 22bit) */
78 #define SUBYPTE_COND_9_22 0
79 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1},
80 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
81 /* Conditional branches.(V850/V850E, max 22bit) */
82 #define SUBYPTE_SA_9_22 2
83 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1},
84 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
85 /* Unconditional branches.(V850/V850E, max 22bit) */
86 #define SUBYPTE_UNCOND_9_22 4
87 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1},
88 {0x1ffffe, -0x200000, 4, 0},
89 /* Conditional branches.(V850E2, max 32bit) */
90 #define SUBYPTE_COND_9_22_32 6
91 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1},
92 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2},
93 {0x7ffffffe, -0x80000000, 8, 0},
94 /* Conditional branches.(V850E2, max 32bit) */
95 #define SUBYPTE_SA_9_22_32 9
96 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1},
97 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2},
98 {0x7ffffffe, -0x80000000, 10, 0},
99 /* Unconditional branches.(V850E2, max 32bit) */
100 #define SUBYPTE_UNCOND_9_22_32 12
101 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1},
102 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2},
103 {0x7ffffffe, -0x80000000, 6, 0},
104 /* Conditional branches.(V850E2R max 22bit) */
105 #define SUBYPTE_COND_9_17_22 15
106 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1},
107 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2},
108 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
109 /* Conditional branches.(V850E2R max 22bit) */
110 #define SUBYPTE_SA_9_17_22 18
111 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1},
112 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2},
113 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
114 /* Conditional branches.(V850E2R max 32bit) */
115 #define SUBYPTE_COND_9_17_22_32 21
116 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1},
117 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2},
118 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3},
119 {0x7ffffffe, -0x80000000, 8, 0},
120 /* Conditional branches.(V850E2R max 32bit) */
121 #define SUBYPTE_SA_9_17_22_32 25
122 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1},
123 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2},
124 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
125 {0x7ffffffe, -0x80000000, 10, 0},
126 /* Loop. (V850E2V4_UP, max 22-bit). */
127 #define SUBYPTE_LOOP_16_22 29
128 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1},
129 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
130 };
131
132 static int v850_relax = 0;
133
134 /* Default branch disp size 22 or 32. */
135 static int default_disp_size = 22;
136
137 /* Default no using bcond17. */
138 static int no_bcond17 = 0;
139
140 /* Default no using ld/st 23bit offset. */
141 static int no_stld23 = 0;
142
143 /* Fixups. */
144 #define MAX_INSN_FIXUPS 5
145
146 struct v850_fixup
147 {
148 expressionS exp;
149 int opindex;
150 bfd_reloc_code_real_type reloc;
151 };
152
153 struct v850_fixup fixups[MAX_INSN_FIXUPS];
154 static int fc;
155
156 struct v850_seg_entry
157 {
158 segT s;
159 const char *name;
160 flagword flags;
161 };
162
163 struct v850_seg_entry v850_seg_table[] =
164 {
165 { NULL, ".sdata",
166 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
167 | SEC_SMALL_DATA },
168 { NULL, ".tdata",
169 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
170 { NULL, ".zdata",
171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
172 { NULL, ".sbss",
173 SEC_ALLOC | SEC_SMALL_DATA },
174 { NULL, ".tbss",
175 SEC_ALLOC },
176 { NULL, ".zbss",
177 SEC_ALLOC},
178 { NULL, ".rosdata",
179 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
180 | SEC_HAS_CONTENTS | SEC_SMALL_DATA },
181 { NULL, ".rozdata",
182 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
183 | SEC_HAS_CONTENTS },
184 { NULL, ".scommon",
185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
186 | SEC_SMALL_DATA | SEC_IS_COMMON },
187 { NULL, ".tcommon",
188 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
189 | SEC_IS_COMMON },
190 { NULL, ".zcommon",
191 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
192 | SEC_IS_COMMON },
193 { NULL, ".call_table_data",
194 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
195 { NULL, ".call_table_text",
196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE
197 | SEC_HAS_CONTENTS},
198 { NULL, ".bss",
199 SEC_ALLOC }
200 };
201
202 #define SDATA_SECTION 0
203 #define TDATA_SECTION 1
204 #define ZDATA_SECTION 2
205 #define SBSS_SECTION 3
206 #define TBSS_SECTION 4
207 #define ZBSS_SECTION 5
208 #define ROSDATA_SECTION 6
209 #define ROZDATA_SECTION 7
210 #define SCOMMON_SECTION 8
211 #define TCOMMON_SECTION 9
212 #define ZCOMMON_SECTION 10
213 #define CALL_TABLE_DATA_SECTION 11
214 #define CALL_TABLE_TEXT_SECTION 12
215 #define BSS_SECTION 13
216
217 static void
do_v850_seg(int i,subsegT sub)218 do_v850_seg (int i, subsegT sub)
219 {
220 struct v850_seg_entry *seg = v850_seg_table + i;
221
222 obj_elf_section_change_hook ();
223
224 if (seg->s != NULL)
225 subseg_set (seg->s, sub);
226 else
227 {
228 seg->s = subseg_new (seg->name, sub);
229 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
230 if ((seg->flags & SEC_LOAD) == 0)
231 seg_info (seg->s)->bss = 1;
232 }
233 }
234
235 static void
v850_seg(int i)236 v850_seg (int i)
237 {
238 subsegT sub = get_absolute_expression ();
239
240 do_v850_seg (i, sub);
241 demand_empty_rest_of_line ();
242 }
243
244 static void
v850_offset(int ignore ATTRIBUTE_UNUSED)245 v850_offset (int ignore ATTRIBUTE_UNUSED)
246 {
247 char *pfrag;
248 int temp = get_absolute_expression ();
249
250 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0,
251 (offsetT) temp, (char *) 0);
252 *pfrag = 0;
253
254 demand_empty_rest_of_line ();
255 }
256
257 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */
258
259 static void
v850_comm(int area)260 v850_comm (int area)
261 {
262 char *name;
263 char c;
264 char *p;
265 int temp;
266 unsigned int size;
267 symbolS *symbolP;
268 int have_align;
269
270 name = input_line_pointer;
271 c = get_symbol_end ();
272
273 /* Just after name is now '\0'. */
274 p = input_line_pointer;
275 *p = c;
276
277 SKIP_WHITESPACE ();
278
279 if (*input_line_pointer != ',')
280 {
281 as_bad (_("Expected comma after symbol-name"));
282 ignore_rest_of_line ();
283 return;
284 }
285
286 /* Skip ','. */
287 input_line_pointer++;
288
289 if ((temp = get_absolute_expression ()) < 0)
290 {
291 /* xgettext:c-format */
292 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp);
293 ignore_rest_of_line ();
294 return;
295 }
296
297 size = temp;
298 *p = 0;
299 symbolP = symbol_find_or_make (name);
300 *p = c;
301
302 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
303 {
304 as_bad (_("Ignoring attempt to re-define symbol"));
305 ignore_rest_of_line ();
306 return;
307 }
308
309 if (S_GET_VALUE (symbolP) != 0)
310 {
311 if (S_GET_VALUE (symbolP) != size)
312 /* xgettext:c-format */
313 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
314 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
315 }
316
317 know (symbol_get_frag (symbolP) == &zero_address_frag);
318
319 if (*input_line_pointer != ',')
320 have_align = 0;
321 else
322 {
323 have_align = 1;
324 input_line_pointer++;
325 SKIP_WHITESPACE ();
326 }
327
328 if (! have_align || *input_line_pointer != '"')
329 {
330 if (! have_align)
331 temp = 0;
332 else
333 {
334 temp = get_absolute_expression ();
335
336 if (temp < 0)
337 {
338 temp = 0;
339 as_warn (_("Common alignment negative; 0 assumed"));
340 }
341 }
342
343 if (symbol_get_obj (symbolP)->local)
344 {
345 segT old_sec;
346 int old_subsec;
347 char *pfrag;
348 int align;
349 flagword applicable;
350
351 old_sec = now_seg;
352 old_subsec = now_subseg;
353
354 applicable = bfd_applicable_section_flags (stdoutput);
355
356 applicable &= SEC_ALLOC;
357
358 switch (area)
359 {
360 case SCOMMON_SECTION:
361 do_v850_seg (SBSS_SECTION, 0);
362 break;
363
364 case ZCOMMON_SECTION:
365 do_v850_seg (ZBSS_SECTION, 0);
366 break;
367
368 case TCOMMON_SECTION:
369 do_v850_seg (TBSS_SECTION, 0);
370 break;
371 }
372
373 if (temp)
374 {
375 /* Convert to a power of 2 alignment. */
376 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align)
377 ;
378
379 if (temp != 1)
380 {
381 as_bad (_("Common alignment not a power of 2"));
382 ignore_rest_of_line ();
383 return;
384 }
385 }
386 else
387 align = 0;
388
389 record_alignment (now_seg, align);
390
391 if (align)
392 frag_align (align, 0, 0);
393
394 switch (area)
395 {
396 case SCOMMON_SECTION:
397 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s)
398 symbol_get_frag (symbolP)->fr_symbol = 0;
399 break;
400
401 case ZCOMMON_SECTION:
402 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s)
403 symbol_get_frag (symbolP)->fr_symbol = 0;
404 break;
405
406 case TCOMMON_SECTION:
407 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s)
408 symbol_get_frag (symbolP)->fr_symbol = 0;
409 break;
410
411 default:
412 abort ();
413 }
414
415 symbol_set_frag (symbolP, frag_now);
416 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
417 (offsetT) size, (char *) 0);
418 *pfrag = 0;
419 S_SET_SIZE (symbolP, size);
420
421 switch (area)
422 {
423 case SCOMMON_SECTION:
424 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s);
425 break;
426
427 case ZCOMMON_SECTION:
428 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s);
429 break;
430
431 case TCOMMON_SECTION:
432 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s);
433 break;
434
435 default:
436 abort ();
437 }
438
439 S_CLEAR_EXTERNAL (symbolP);
440 obj_elf_section_change_hook ();
441 subseg_set (old_sec, old_subsec);
442 }
443 else
444 {
445 segT old_sec;
446 int old_subsec;
447
448 allocate_common:
449 old_sec = now_seg;
450 old_subsec = now_subseg;
451
452 S_SET_VALUE (symbolP, (valueT) size);
453 S_SET_ALIGN (symbolP, temp);
454 S_SET_EXTERNAL (symbolP);
455
456 switch (area)
457 {
458 case SCOMMON_SECTION:
459 case ZCOMMON_SECTION:
460 case TCOMMON_SECTION:
461 do_v850_seg (area, 0);
462 S_SET_SEGMENT (symbolP, v850_seg_table[area].s);
463 break;
464
465 default:
466 abort ();
467 }
468
469 obj_elf_section_change_hook ();
470 subseg_set (old_sec, old_subsec);
471 }
472 }
473 else
474 {
475 input_line_pointer++;
476
477 /* @@ Some use the dot, some don't. Can we get some consistency?? */
478 if (*input_line_pointer == '.')
479 input_line_pointer++;
480
481 /* @@ Some say data, some say bss. */
482 if (strncmp (input_line_pointer, "bss\"", 4)
483 && strncmp (input_line_pointer, "data\"", 5))
484 {
485 while (*--input_line_pointer != '"')
486 ;
487 input_line_pointer--;
488 goto bad_common_segment;
489 }
490
491 while (*input_line_pointer++ != '"')
492 ;
493
494 goto allocate_common;
495 }
496
497 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
498
499 demand_empty_rest_of_line ();
500 return;
501
502 {
503 bad_common_segment:
504 p = input_line_pointer;
505 while (*p && *p != '\n')
506 p++;
507 c = *p;
508 *p = '\0';
509 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
510 *p = c;
511 input_line_pointer = p;
512 ignore_rest_of_line ();
513 return;
514 }
515 }
516
517 static void
set_machine(int number)518 set_machine (int number)
519 {
520 machine = number;
521 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
522
523 switch (machine)
524 {
525 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
526 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
527 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
528 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
529 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break;
530 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
531 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break;
532 }
533 }
534
535 static void
v850_longcode(int type)536 v850_longcode (int type)
537 {
538 expressionS ex;
539
540 if (! v850_relax)
541 {
542 if (type == 1)
543 as_warn (_(".longcall pseudo-op seen when not relaxing"));
544 else
545 as_warn (_(".longjump pseudo-op seen when not relaxing"));
546 }
547
548 expression (&ex);
549
550 if (ex.X_op != O_symbol || ex.X_add_number != 0)
551 {
552 as_bad (_("bad .longcall format"));
553 ignore_rest_of_line ();
554
555 return;
556 }
557
558 if (type == 1)
559 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
560 BFD_RELOC_V850_LONGCALL);
561 else
562 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
563 BFD_RELOC_V850_LONGJUMP);
564
565 demand_empty_rest_of_line ();
566 }
567
568 /* The target specific pseudo-ops which we support. */
569 const pseudo_typeS md_pseudo_table[] =
570 {
571 { "sdata", v850_seg, SDATA_SECTION },
572 { "tdata", v850_seg, TDATA_SECTION },
573 { "zdata", v850_seg, ZDATA_SECTION },
574 { "sbss", v850_seg, SBSS_SECTION },
575 { "tbss", v850_seg, TBSS_SECTION },
576 { "zbss", v850_seg, ZBSS_SECTION },
577 { "rosdata", v850_seg, ROSDATA_SECTION },
578 { "rozdata", v850_seg, ROZDATA_SECTION },
579 { "bss", v850_seg, BSS_SECTION },
580 { "offset", v850_offset, 0 },
581 { "word", cons, 4 },
582 { "zcomm", v850_comm, ZCOMMON_SECTION },
583 { "scomm", v850_comm, SCOMMON_SECTION },
584 { "tcomm", v850_comm, TCOMMON_SECTION },
585 { "v850", set_machine, 0 },
586 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
587 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
588 { "v850e", set_machine, bfd_mach_v850e },
589 { "v850e1", set_machine, bfd_mach_v850e1 },
590 { "v850e2", set_machine, bfd_mach_v850e2 },
591 { "v850e2v3", set_machine, bfd_mach_v850e2v3 },
592 { "v850e2v4", set_machine, bfd_mach_v850e3v5 },
593 { "v850e3v5", set_machine, bfd_mach_v850e3v5 },
594 { "longcall", v850_longcode, 1 },
595 { "longjump", v850_longcode, 2 },
596 { NULL, NULL, 0 }
597 };
598
599 /* Opcode hash table. */
600 static struct hash_control *v850_hash;
601
602 /* This table is sorted. Suitable for searching by a binary search. */
603 static const struct reg_name pre_defined_registers[] =
604 {
605 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */
606 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */
607 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */
608 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */
609 { "r0", 0, PROCESSOR_ALL },
610 { "r1", 1, PROCESSOR_ALL },
611 { "r10", 10, PROCESSOR_ALL },
612 { "r11", 11, PROCESSOR_ALL },
613 { "r12", 12, PROCESSOR_ALL },
614 { "r13", 13, PROCESSOR_ALL },
615 { "r14", 14, PROCESSOR_ALL },
616 { "r15", 15, PROCESSOR_ALL },
617 { "r16", 16, PROCESSOR_ALL },
618 { "r17", 17, PROCESSOR_ALL },
619 { "r18", 18, PROCESSOR_ALL },
620 { "r19", 19, PROCESSOR_ALL },
621 { "r2", 2, PROCESSOR_ALL },
622 { "r20", 20, PROCESSOR_ALL },
623 { "r21", 21, PROCESSOR_ALL },
624 { "r22", 22, PROCESSOR_ALL },
625 { "r23", 23, PROCESSOR_ALL },
626 { "r24", 24, PROCESSOR_ALL },
627 { "r25", 25, PROCESSOR_ALL },
628 { "r26", 26, PROCESSOR_ALL },
629 { "r27", 27, PROCESSOR_ALL },
630 { "r28", 28, PROCESSOR_ALL },
631 { "r29", 29, PROCESSOR_ALL },
632 { "r3", 3, PROCESSOR_ALL },
633 { "r30", 30, PROCESSOR_ALL },
634 { "r31", 31, PROCESSOR_ALL },
635 { "r4", 4, PROCESSOR_ALL },
636 { "r5", 5, PROCESSOR_ALL },
637 { "r6", 6, PROCESSOR_ALL },
638 { "r7", 7, PROCESSOR_ALL },
639 { "r8", 8, PROCESSOR_ALL },
640 { "r9", 9, PROCESSOR_ALL },
641 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */
642 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */
643 { "zero", 0, PROCESSOR_ALL },
644 };
645
646 #define REG_NAME_CNT \
647 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
648
649 static const struct reg_name system_registers[] =
650 {
651 { "asid", 23, PROCESSOR_NOT_V850 },
652 { "bpam", 25, PROCESSOR_NOT_V850 },
653 { "bpav", 24, PROCESSOR_NOT_V850 },
654 { "bpc", 22, PROCESSOR_NOT_V850 },
655 { "bpdm", 27, PROCESSOR_NOT_V850 },
656 { "bpdv", 26, PROCESSOR_NOT_V850 },
657 { "bsel", 31, PROCESSOR_V850E2_UP },
658 { "cfg", 7, PROCESSOR_V850E2V3_UP },
659 { "ctbp", 20, PROCESSOR_NOT_V850 },
660 { "ctpc", 16, PROCESSOR_NOT_V850 },
661 { "ctpsw", 17, PROCESSOR_NOT_V850 },
662 { "dbic", 15, PROCESSOR_V850E2_UP },
663 { "dbpc", 18, PROCESSOR_NOT_V850 },
664 { "dbpsw", 19, PROCESSOR_NOT_V850 },
665 { "dbwr", 30, PROCESSOR_V850E2_UP },
666 { "dir", 21, PROCESSOR_NOT_V850 },
667 { "dpa0l", 16, PROCESSOR_V850E2V3_UP },
668 { "dpa0u", 17, PROCESSOR_V850E2V3_UP },
669 { "dpa1l", 18, PROCESSOR_V850E2V3_UP },
670 { "dpa1u", 19, PROCESSOR_V850E2V3_UP },
671 { "dpa2l", 20, PROCESSOR_V850E2V3_UP },
672 { "dpa2u", 21, PROCESSOR_V850E2V3_UP },
673 { "dpa3l", 22, PROCESSOR_V850E2V3_UP },
674 { "dpa3u", 23, PROCESSOR_V850E2V3_UP },
675 { "dpa4l", 24, PROCESSOR_V850E2V3_UP },
676 { "dpa4u", 25, PROCESSOR_V850E2V3_UP },
677 { "dpa5l", 26, PROCESSOR_V850E2V3_UP },
678 { "dpa5u", 27, PROCESSOR_V850E2V3_UP },
679 { "ecr", 4, PROCESSOR_ALL },
680 { "eh_base", 3, PROCESSOR_V850E2V3_UP },
681 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP },
682 { "eh_reset", 2, PROCESSOR_V850E2V3_UP },
683 { "eiic", 13, PROCESSOR_V850E2_UP },
684 { "eipc", 0, PROCESSOR_ALL },
685 { "eipsw", 1, PROCESSOR_ALL },
686 { "eiwr", 28, PROCESSOR_V850E2_UP },
687 { "feic", 14, PROCESSOR_V850E2_UP },
688 { "fepc", 2, PROCESSOR_ALL },
689 { "fepsw", 3, PROCESSOR_ALL },
690 { "fewr", 29, PROCESSOR_V850E2_UP },
691 { "fpcc", 9, PROCESSOR_V850E2V3_UP },
692 { "fpcfg", 10, PROCESSOR_V850E2V3_UP },
693 { "fpec", 11, PROCESSOR_V850E2V3_UP },
694 { "fpepc", 7, PROCESSOR_V850E2V3_UP },
695 { "fpspc", 27, PROCESSOR_V850E2V3_UP },
696 { "fpsr", 6, PROCESSOR_V850E2V3_UP },
697 { "fpst", 8, PROCESSOR_V850E2V3_UP },
698 { "ipa0l", 6, PROCESSOR_V850E2V3_UP },
699 { "ipa0u", 7, PROCESSOR_V850E2V3_UP },
700 { "ipa1l", 8, PROCESSOR_V850E2V3_UP },
701 { "ipa1u", 9, PROCESSOR_V850E2V3_UP },
702 { "ipa2l", 10, PROCESSOR_V850E2V3_UP },
703 { "ipa2u", 11, PROCESSOR_V850E2V3_UP },
704 { "ipa3l", 12, PROCESSOR_V850E2V3_UP },
705 { "ipa3u", 13, PROCESSOR_V850E2V3_UP },
706 { "ipa4l", 14, PROCESSOR_V850E2V3_UP },
707 { "ipa4u", 15, PROCESSOR_V850E2V3_UP },
708 { "mca", 24, PROCESSOR_V850E2V3_UP },
709 { "mcc", 26, PROCESSOR_V850E2V3_UP },
710 { "mcr", 27, PROCESSOR_V850E2V3_UP },
711 { "mcs", 25, PROCESSOR_V850E2V3_UP },
712 { "mpc", 1, PROCESSOR_V850E2V3_UP },
713 { "mpm", 0, PROCESSOR_V850E2V3_UP },
714 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP },
715 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP },
716 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP },
717 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP },
718 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP },
719 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP },
720 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP },
721 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP },
722 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP },
723 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP },
724 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP },
725 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP },
726 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP },
727 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP },
728 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP },
729 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP },
730 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP },
731 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP },
732 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP },
733 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP },
734 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP },
735 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP },
736 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP },
737 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP },
738 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP },
739 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP },
740 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP },
741 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP },
742 { "pid", 6, PROCESSOR_V850E2V3_UP },
743 { "pmcr0", 4, PROCESSOR_V850E2V3_UP },
744 { "pmis2", 14, PROCESSOR_V850E2V3_UP },
745 { "psw", 5, PROCESSOR_ALL },
746 { "scbp", 12, PROCESSOR_V850E2V3_UP },
747 { "sccfg", 11, PROCESSOR_V850E2V3_UP },
748 { "sr0", 0, PROCESSOR_ALL },
749 { "sr1", 1, PROCESSOR_ALL },
750 { "sr10", 10, PROCESSOR_ALL },
751 { "sr11", 11, PROCESSOR_ALL },
752 { "sr12", 12, PROCESSOR_ALL },
753 { "sr13", 13, PROCESSOR_ALL },
754 { "sr14", 14, PROCESSOR_ALL },
755 { "sr15", 15, PROCESSOR_ALL },
756 { "sr16", 16, PROCESSOR_ALL },
757 { "sr17", 17, PROCESSOR_ALL },
758 { "sr18", 18, PROCESSOR_ALL },
759 { "sr19", 19, PROCESSOR_ALL },
760 { "sr2", 2, PROCESSOR_ALL },
761 { "sr20", 20, PROCESSOR_ALL },
762 { "sr21", 21, PROCESSOR_ALL },
763 { "sr22", 22, PROCESSOR_ALL },
764 { "sr23", 23, PROCESSOR_ALL },
765 { "sr24", 24, PROCESSOR_ALL },
766 { "sr25", 25, PROCESSOR_ALL },
767 { "sr26", 26, PROCESSOR_ALL },
768 { "sr27", 27, PROCESSOR_ALL },
769 { "sr28", 28, PROCESSOR_ALL },
770 { "sr29", 29, PROCESSOR_ALL },
771 { "sr3", 3, PROCESSOR_ALL },
772 { "sr30", 30, PROCESSOR_ALL },
773 { "sr31", 31, PROCESSOR_ALL },
774 { "sr4", 4, PROCESSOR_ALL },
775 { "sr5", 5, PROCESSOR_ALL },
776 { "sr6", 6, PROCESSOR_ALL },
777 { "sr7", 7, PROCESSOR_ALL },
778 { "sr8", 8, PROCESSOR_ALL },
779 { "sr9", 9, PROCESSOR_ALL },
780 { "sw_base", 3, PROCESSOR_V850E2V3_UP },
781 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP },
782 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP },
783 { "tid", 2, PROCESSOR_V850E2V3_UP },
784 { "vmadr", 6, PROCESSOR_V850E2V3_UP },
785 { "vmecr", 4, PROCESSOR_V850E2V3_UP },
786 { "vmtid", 5, PROCESSOR_V850E2V3_UP },
787 { "vsadr", 2, PROCESSOR_V850E2V3_UP },
788 { "vsecr", 0, PROCESSOR_V850E2V3_UP },
789 { "vstid", 1, PROCESSOR_V850E2V3_UP },
790 };
791
792 #define SYSREG_NAME_CNT \
793 (sizeof (system_registers) / sizeof (struct reg_name))
794
795
796 static const struct reg_name cc_names[] =
797 {
798 { "c", 0x1, PROCESSOR_ALL },
799 { "e", 0x2, PROCESSOR_ALL },
800 { "ge", 0xe, PROCESSOR_ALL },
801 { "gt", 0xf, PROCESSOR_ALL },
802 { "h", 0xb, PROCESSOR_ALL },
803 { "l", 0x1, PROCESSOR_ALL },
804 { "le", 0x7, PROCESSOR_ALL },
805 { "lt", 0x6, PROCESSOR_ALL },
806 { "n", 0x4, PROCESSOR_ALL },
807 { "nc", 0x9, PROCESSOR_ALL },
808 { "ne", 0xa, PROCESSOR_ALL },
809 { "nh", 0x3, PROCESSOR_ALL },
810 { "nl", 0x9, PROCESSOR_ALL },
811 { "ns", 0xc, PROCESSOR_ALL },
812 { "nv", 0x8, PROCESSOR_ALL },
813 { "nz", 0xa, PROCESSOR_ALL },
814 { "p", 0xc, PROCESSOR_ALL },
815 { "s", 0x4, PROCESSOR_ALL },
816 #define COND_SA_NUM 0xd
817 { "sa", COND_SA_NUM, PROCESSOR_ALL },
818 { "t", 0x5, PROCESSOR_ALL },
819 { "v", 0x0, PROCESSOR_ALL },
820 { "z", 0x2, PROCESSOR_ALL },
821 };
822
823 #define CC_NAME_CNT \
824 (sizeof (cc_names) / sizeof (struct reg_name))
825
826 static const struct reg_name float_cc_names[] =
827 {
828 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */
829 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */
830 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */
831 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */
832 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */
833 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */
834 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */
835 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */
836 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */
837 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */
838 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */
839 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */
840 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */
841 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */
842 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */
843 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */
844 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */
845 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */
846 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */
847 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */
848 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */
849 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */
850 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */
851 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */
852 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */
853 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */
854 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */
855 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */
856 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */
857 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */
858 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */
859 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */
860 };
861
862 #define FLOAT_CC_NAME_CNT \
863 (sizeof (float_cc_names) / sizeof (struct reg_name))
864
865
866 static const struct reg_name cacheop_names[] =
867 {
868 { "cfald", 0x44, PROCESSOR_V850E3V5_UP },
869 { "cfali", 0x40, PROCESSOR_V850E3V5_UP },
870 { "chbid", 0x04, PROCESSOR_V850E3V5_UP },
871 { "chbii", 0x00, PROCESSOR_V850E3V5_UP },
872 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP },
873 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP },
874 { "cibid", 0x24, PROCESSOR_V850E3V5_UP },
875 { "cibii", 0x20, PROCESSOR_V850E3V5_UP },
876 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP },
877 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP },
878 { "cildd", 0x65, PROCESSOR_V850E3V5_UP },
879 { "cildi", 0x61, PROCESSOR_V850E3V5_UP },
880 { "cistd", 0x64, PROCESSOR_V850E3V5_UP },
881 { "cisti", 0x60, PROCESSOR_V850E3V5_UP },
882 };
883
884 #define CACHEOP_NAME_CNT \
885 (sizeof (cacheop_names) / sizeof (struct reg_name))
886
887 static const struct reg_name prefop_names[] =
888 {
889 { "prefd", 0x04, PROCESSOR_V850E3V5_UP },
890 { "prefi", 0x00, PROCESSOR_V850E3V5_UP },
891 };
892
893 #define PREFOP_NAME_CNT \
894 (sizeof (prefop_names) / sizeof (struct reg_name))
895
896 static const struct reg_name vector_registers[] =
897 {
898 { "vr0", 0, PROCESSOR_V850E3V5_UP },
899 { "vr1", 1, PROCESSOR_V850E3V5_UP },
900 { "vr10", 10, PROCESSOR_V850E3V5_UP },
901 { "vr11", 11, PROCESSOR_V850E3V5_UP },
902 { "vr12", 12, PROCESSOR_V850E3V5_UP },
903 { "vr13", 13, PROCESSOR_V850E3V5_UP },
904 { "vr14", 14, PROCESSOR_V850E3V5_UP },
905 { "vr15", 15, PROCESSOR_V850E3V5_UP },
906 { "vr16", 16, PROCESSOR_V850E3V5_UP },
907 { "vr17", 17, PROCESSOR_V850E3V5_UP },
908 { "vr18", 18, PROCESSOR_V850E3V5_UP },
909 { "vr19", 19, PROCESSOR_V850E3V5_UP },
910 { "vr2", 2, PROCESSOR_V850E3V5_UP },
911 { "vr20", 20, PROCESSOR_V850E3V5_UP },
912 { "vr21", 21, PROCESSOR_V850E3V5_UP },
913 { "vr22", 22, PROCESSOR_V850E3V5_UP },
914 { "vr23", 23, PROCESSOR_V850E3V5_UP },
915 { "vr24", 24, PROCESSOR_V850E3V5_UP },
916 { "vr25", 25, PROCESSOR_V850E3V5_UP },
917 { "vr26", 26, PROCESSOR_V850E3V5_UP },
918 { "vr27", 27, PROCESSOR_V850E3V5_UP },
919 { "vr28", 28, PROCESSOR_V850E3V5_UP },
920 { "vr29", 29, PROCESSOR_V850E3V5_UP },
921 { "vr3", 3, PROCESSOR_V850E3V5_UP },
922 { "vr30", 30, PROCESSOR_V850E3V5_UP },
923 { "vr31", 31, PROCESSOR_V850E3V5_UP },
924 { "vr4", 4, PROCESSOR_V850E3V5_UP },
925 { "vr5", 5, PROCESSOR_V850E3V5_UP },
926 { "vr6", 6, PROCESSOR_V850E3V5_UP },
927 { "vr7", 7, PROCESSOR_V850E3V5_UP },
928 { "vr8", 8, PROCESSOR_V850E3V5_UP },
929 { "vr9", 9, PROCESSOR_V850E3V5_UP },
930 };
931
932 #define VREG_NAME_CNT \
933 (sizeof (vector_registers) / sizeof (struct reg_name))
934
935 /* Do a binary search of the given register table to see if NAME is a
936 valid regiter name. Return the register number from the array on
937 success, or -1 on failure. */
938
939 static int
reg_name_search(const struct reg_name * regs,int regcount,const char * name,bfd_boolean accept_numbers)940 reg_name_search (const struct reg_name *regs,
941 int regcount,
942 const char *name,
943 bfd_boolean accept_numbers)
944 {
945 int middle, low, high;
946 int cmp;
947 symbolS *symbolP;
948
949 /* If the register name is a symbol, then evaluate it. */
950 if ((symbolP = symbol_find (name)) != NULL)
951 {
952 /* If the symbol is an alias for another name then use that.
953 If the symbol is an alias for a number, then return the number. */
954 if (symbol_equated_p (symbolP))
955 name
956 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
957 else if (accept_numbers)
958 {
959 int reg = S_GET_VALUE (symbolP);
960 return reg;
961 }
962
963 /* Otherwise drop through and try parsing name normally. */
964 }
965
966 low = 0;
967 high = regcount - 1;
968
969 do
970 {
971 middle = (low + high) / 2;
972 cmp = strcasecmp (name, regs[middle].name);
973 if (cmp < 0)
974 high = middle - 1;
975 else if (cmp > 0)
976 low = middle + 1;
977 else
978 return ((regs[middle].processors & processor_mask)
979 ? regs[middle].value
980 : -1);
981 }
982 while (low <= high);
983 return -1;
984 }
985
986 /* Summary of register_name().
987
988 in: Input_line_pointer points to 1st char of operand.
989
990 out: An expressionS.
991 The operand may have been a register: in this case, X_op == O_register,
992 X_add_number is set to the register number, and truth is returned.
993 Input_line_pointer->(next non-blank) char after operand, or is in
994 its original state. */
995
996 static bfd_boolean
register_name(expressionS * expressionP)997 register_name (expressionS *expressionP)
998 {
999 int reg_number;
1000 char *name;
1001 char *start;
1002 char c;
1003
1004 /* Find the spelling of the operand. */
1005 start = name = input_line_pointer;
1006
1007 c = get_symbol_end ();
1008
1009 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
1010 name, FALSE);
1011
1012 /* Put back the delimiting char. */
1013 *input_line_pointer = c;
1014
1015 expressionP->X_add_symbol = NULL;
1016 expressionP->X_op_symbol = NULL;
1017
1018 /* Look to see if it's in the register table. */
1019 if (reg_number >= 0)
1020 {
1021 expressionP->X_op = O_register;
1022 expressionP->X_add_number = reg_number;
1023
1024 return TRUE;
1025 }
1026
1027 /* Reset the line as if we had not done anything. */
1028 input_line_pointer = start;
1029
1030 expressionP->X_op = O_illegal;
1031
1032 return FALSE;
1033 }
1034
1035 /* Summary of system_register_name().
1036
1037 in: INPUT_LINE_POINTER points to 1st char of operand.
1038 EXPRESSIONP points to an expression structure to be filled in.
1039 ACCEPT_NUMBERS is true iff numerical register names may be used.
1040
1041 out: An expressionS structure in expressionP.
1042 The operand may have been a register: in this case, X_op == O_register,
1043 X_add_number is set to the register number, and truth is returned.
1044 Input_line_pointer->(next non-blank) char after operand, or is in
1045 its original state. */
1046
1047 static bfd_boolean
system_register_name(expressionS * expressionP,bfd_boolean accept_numbers)1048 system_register_name (expressionS *expressionP,
1049 bfd_boolean accept_numbers)
1050 {
1051 int reg_number;
1052 char *name;
1053 char *start;
1054 char c;
1055
1056 /* Find the spelling of the operand. */
1057 start = name = input_line_pointer;
1058
1059 c = get_symbol_end ();
1060 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name,
1061 accept_numbers);
1062
1063 /* Put back the delimiting char. */
1064 *input_line_pointer = c;
1065
1066 if (reg_number < 0
1067 && accept_numbers)
1068 {
1069 /* Reset input_line pointer. */
1070 input_line_pointer = start;
1071
1072 if (ISDIGIT (*input_line_pointer))
1073 {
1074 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1075 }
1076 }
1077
1078 expressionP->X_add_symbol = NULL;
1079 expressionP->X_op_symbol = NULL;
1080
1081 /* Look to see if it's in the register table. */
1082 if (reg_number >= 0)
1083 {
1084 expressionP->X_op = O_register;
1085 expressionP->X_add_number = reg_number;
1086
1087 return TRUE;
1088 }
1089
1090 /* Reset the line as if we had not done anything. */
1091 input_line_pointer = start;
1092
1093 expressionP->X_op = O_illegal;
1094
1095 return FALSE;
1096 }
1097
1098 /* Summary of cc_name().
1099
1100 in: INPUT_LINE_POINTER points to 1st char of operand.
1101
1102 out: An expressionS.
1103 The operand may have been a register: in this case, X_op == O_register,
1104 X_add_number is set to the register number, and truth is returned.
1105 Input_line_pointer->(next non-blank) char after operand, or is in
1106 its original state. */
1107
1108 static bfd_boolean
cc_name(expressionS * expressionP,bfd_boolean accept_numbers)1109 cc_name (expressionS *expressionP,
1110 bfd_boolean accept_numbers)
1111 {
1112 int reg_number;
1113 char *name;
1114 char *start;
1115 char c;
1116
1117 /* Find the spelling of the operand. */
1118 start = name = input_line_pointer;
1119
1120 c = get_symbol_end ();
1121 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers);
1122
1123 /* Put back the delimiting char. */
1124 *input_line_pointer = c;
1125
1126 if (reg_number < 0
1127 && accept_numbers)
1128 {
1129 /* Reset input_line pointer. */
1130 input_line_pointer = start;
1131
1132 if (ISDIGIT (*input_line_pointer))
1133 {
1134 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1135 }
1136 }
1137
1138 expressionP->X_add_symbol = NULL;
1139 expressionP->X_op_symbol = NULL;
1140
1141 /* Look to see if it's in the register table. */
1142 if (reg_number >= 0)
1143 {
1144 expressionP->X_op = O_constant;
1145 expressionP->X_add_number = reg_number;
1146
1147 return TRUE;
1148 }
1149
1150 /* Reset the line as if we had not done anything. */
1151 input_line_pointer = start;
1152
1153 expressionP->X_op = O_illegal;
1154 expressionP->X_add_number = 0;
1155
1156 return FALSE;
1157 }
1158
1159 static bfd_boolean
float_cc_name(expressionS * expressionP,bfd_boolean accept_numbers)1160 float_cc_name (expressionS *expressionP,
1161 bfd_boolean accept_numbers)
1162 {
1163 int reg_number;
1164 char *name;
1165 char *start;
1166 char c;
1167
1168 /* Find the spelling of the operand. */
1169 start = name = input_line_pointer;
1170
1171 c = get_symbol_end ();
1172 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers);
1173
1174 /* Put back the delimiting char. */
1175 *input_line_pointer = c;
1176
1177 if (reg_number < 0
1178 && accept_numbers)
1179 {
1180 /* Reset input_line pointer. */
1181 input_line_pointer = start;
1182
1183 if (ISDIGIT (*input_line_pointer))
1184 {
1185 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1186 }
1187 }
1188
1189 expressionP->X_add_symbol = NULL;
1190 expressionP->X_op_symbol = NULL;
1191
1192 /* Look to see if it's in the register table. */
1193 if (reg_number >= 0)
1194 {
1195 expressionP->X_op = O_constant;
1196 expressionP->X_add_number = reg_number;
1197
1198 return TRUE;
1199 }
1200
1201 /* Reset the line as if we had not done anything. */
1202 input_line_pointer = start;
1203
1204 expressionP->X_op = O_illegal;
1205 expressionP->X_add_number = 0;
1206
1207 return FALSE;
1208 }
1209
1210 static bfd_boolean
cacheop_name(expressionS * expressionP,bfd_boolean accept_numbers)1211 cacheop_name (expressionS * expressionP,
1212 bfd_boolean accept_numbers)
1213 {
1214 int reg_number;
1215 char *name;
1216 char *start;
1217 char c;
1218
1219 /* Find the spelling of the operand. */
1220 start = name = input_line_pointer;
1221
1222 c = get_symbol_end ();
1223 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers);
1224
1225 /* Put back the delimiting char. */
1226 *input_line_pointer = c;
1227
1228 if (reg_number < 0
1229 && accept_numbers)
1230 {
1231 /* Reset input_line pointer. */
1232 input_line_pointer = start;
1233
1234 if (ISDIGIT (*input_line_pointer))
1235 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1236 }
1237
1238 expressionP->X_add_symbol = NULL;
1239 expressionP->X_op_symbol = NULL;
1240
1241 /* Look to see if it's in the register table. */
1242 if (reg_number >= 0)
1243 {
1244 expressionP->X_op = O_constant;
1245 expressionP->X_add_number = reg_number;
1246
1247 return TRUE;
1248 }
1249
1250 /* Reset the line as if we had not done anything. */
1251 input_line_pointer = start;
1252
1253 expressionP->X_op = O_illegal;
1254 expressionP->X_add_number = 0;
1255
1256 return FALSE;
1257 }
1258
1259 static bfd_boolean
prefop_name(expressionS * expressionP,bfd_boolean accept_numbers)1260 prefop_name (expressionS * expressionP,
1261 bfd_boolean accept_numbers)
1262 {
1263 int reg_number;
1264 char *name;
1265 char *start;
1266 char c;
1267
1268 /* Find the spelling of the operand. */
1269 start = name = input_line_pointer;
1270
1271 c = get_symbol_end ();
1272 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers);
1273
1274 /* Put back the delimiting char. */
1275 *input_line_pointer = c;
1276
1277 if (reg_number < 0
1278 && accept_numbers)
1279 {
1280 /* Reset input_line pointer. */
1281 input_line_pointer = start;
1282
1283 if (ISDIGIT (*input_line_pointer))
1284 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1285 }
1286
1287 expressionP->X_add_symbol = NULL;
1288 expressionP->X_op_symbol = NULL;
1289
1290 /* Look to see if it's in the register table. */
1291 if (reg_number >= 0)
1292 {
1293 expressionP->X_op = O_constant;
1294 expressionP->X_add_number = reg_number;
1295
1296 return TRUE;
1297 }
1298
1299 /* Reset the line as if we had not done anything. */
1300 input_line_pointer = start;
1301
1302 expressionP->X_op = O_illegal;
1303 expressionP->X_add_number = 0;
1304
1305 return FALSE;
1306 }
1307
1308 static bfd_boolean
vector_register_name(expressionS * expressionP)1309 vector_register_name (expressionS *expressionP)
1310 {
1311 int reg_number;
1312 char *name;
1313 char *start;
1314 char c;
1315
1316 /* Find the spelling of the operand. */
1317 start = name = input_line_pointer;
1318
1319 c = get_symbol_end ();
1320
1321 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT,
1322 name, FALSE);
1323
1324 /* Put back the delimiting char. */
1325 *input_line_pointer = c;
1326
1327 expressionP->X_add_symbol = NULL;
1328 expressionP->X_op_symbol = NULL;
1329
1330 /* Look to see if it's in the register table. */
1331 if (reg_number >= 0)
1332 {
1333 expressionP->X_op = O_register;
1334 expressionP->X_add_number = reg_number;
1335
1336 return TRUE;
1337 }
1338
1339 /* Reset the line as if we had not done anything. */
1340 input_line_pointer = start;
1341
1342 expressionP->X_op = O_illegal;
1343
1344 return FALSE;
1345 }
1346
1347 static void
skip_white_space(void)1348 skip_white_space (void)
1349 {
1350 while (*input_line_pointer == ' '
1351 || *input_line_pointer == '\t')
1352 ++input_line_pointer;
1353 }
1354
1355 /* Summary of parse_register_list ().
1356
1357 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
1358 INSN is the partially constructed instruction.
1359 OPERAND is the operand being inserted.
1360
1361 out: NULL if the parse completed successfully, otherwise a
1362 pointer to an error message is returned. If the parse
1363 completes the correct bit fields in the instruction
1364 will be filled in.
1365
1366 Parses register lists with the syntax:
1367
1368 { rX }
1369 { rX, rY }
1370 { rX - rY }
1371 { rX - rY, rZ }
1372 etc
1373
1374 and also parses constant expressions whoes bits indicate the
1375 registers in the lists. The LSB in the expression refers to
1376 the lowest numbered permissible register in the register list,
1377 and so on upwards. System registers are considered to be very
1378 high numbers. */
1379
1380 static char *
parse_register_list(unsigned long * insn,const struct v850_operand * operand)1381 parse_register_list (unsigned long *insn,
1382 const struct v850_operand *operand)
1383 {
1384 static int type1_regs[32] =
1385 {
1386 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1387 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1388 };
1389
1390 int *regs;
1391 expressionS exp;
1392
1393 /* Select a register array to parse. */
1394 switch (operand->shift)
1395 {
1396 case 0xffe00001: regs = type1_regs; break;
1397 default:
1398 as_bad (_("unknown operand shift: %x\n"), operand->shift);
1399 return _("internal failure in parse_register_list");
1400 }
1401
1402 skip_white_space ();
1403
1404 /* If the expression starts with a curly brace it is a register list.
1405 Otherwise it is a constant expression, whoes bits indicate which
1406 registers are to be included in the list. */
1407 if (*input_line_pointer != '{')
1408 {
1409 int reg;
1410 int i;
1411
1412 expression (&exp);
1413
1414 if (exp.X_op != O_constant)
1415 return _("constant expression or register list expected");
1416
1417 if (regs == type1_regs)
1418 {
1419 if (exp.X_add_number & 0xFFFFF000)
1420 return _("high bits set in register list expression");
1421
1422 for (reg = 20; reg < 32; reg++)
1423 if (exp.X_add_number & (1 << (reg - 20)))
1424 {
1425 for (i = 0; i < 32; i++)
1426 if (regs[i] == reg)
1427 *insn |= (1 << i);
1428 }
1429 }
1430
1431 return NULL;
1432 }
1433
1434 input_line_pointer++;
1435
1436 /* Parse the register list until a terminator (closing curly brace or
1437 new-line) is found. */
1438 for (;;)
1439 {
1440 skip_white_space ();
1441
1442 if (register_name (&exp))
1443 {
1444 int i;
1445
1446 /* Locate the given register in the list, and if it is there,
1447 insert the corresponding bit into the instruction. */
1448 for (i = 0; i < 32; i++)
1449 {
1450 if (regs[i] == exp.X_add_number)
1451 {
1452 *insn |= (1 << i);
1453 break;
1454 }
1455 }
1456
1457 if (i == 32)
1458 return _("illegal register included in list");
1459 }
1460 else if (system_register_name (&exp, TRUE))
1461 {
1462 if (regs == type1_regs)
1463 {
1464 return _("system registers cannot be included in list");
1465 }
1466 }
1467
1468 if (*input_line_pointer == '}')
1469 {
1470 input_line_pointer++;
1471 break;
1472 }
1473 else if (*input_line_pointer == ',')
1474 {
1475 input_line_pointer++;
1476 continue;
1477 }
1478 else if (*input_line_pointer == '-')
1479 {
1480 /* We have encountered a range of registers: rX - rY. */
1481 int j;
1482 expressionS exp2;
1483
1484 /* Skip the dash. */
1485 ++input_line_pointer;
1486
1487 /* Get the second register in the range. */
1488 if (! register_name (&exp2))
1489 {
1490 return _("second register should follow dash in register list");
1491 }
1492
1493 if (exp.X_add_number > exp2.X_add_number)
1494 {
1495 return _("second register should be greater than first register");
1496 }
1497
1498 /* Add the rest of the registers in the range. */
1499 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++)
1500 {
1501 int i;
1502
1503 /* Locate the given register in the list, and if it is there,
1504 insert the corresponding bit into the instruction. */
1505 for (i = 0; i < 32; i++)
1506 {
1507 if (regs[i] == j)
1508 {
1509 *insn |= (1 << i);
1510 break;
1511 }
1512 }
1513
1514 if (i == 32)
1515 return _("illegal register included in list");
1516 }
1517
1518 exp = exp2;
1519 }
1520 else
1521 break;
1522 }
1523
1524 return NULL;
1525 }
1526
1527 const char *md_shortopts = "m:";
1528
1529 struct option md_longopts[] =
1530 {
1531 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1532 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22},
1533 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1534 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
1535 {NULL, no_argument, NULL, 0}
1536 };
1537
1538 size_t md_longopts_size = sizeof (md_longopts);
1539
1540 void
md_show_usage(FILE * stream)1541 md_show_usage (FILE *stream)
1542 {
1543 fprintf (stream, _(" V850 options:\n"));
1544 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1545 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1546 fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
1547 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
1548 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
1549 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n"));
1550 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
1551 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n"));
1552 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n"));
1553 fprintf (stream, _(" -mrelax Enable relaxation\n"));
1554 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1555 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1556 fprintf (stream, _(" -mextension enable extension opcode support\n"));
1557 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1558 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
1559 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n"));
1560 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n"));
1561 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n"));
1562 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n"));
1563 }
1564
1565 int
md_parse_option(int c,char * arg)1566 md_parse_option (int c, char *arg)
1567 {
1568 if (c != 'm')
1569 {
1570 switch (c)
1571 {
1572 case OPTION_DISP_SIZE_DEFAULT_22:
1573 default_disp_size = 22;
1574 return 1;
1575
1576 case OPTION_DISP_SIZE_DEFAULT_32:
1577 default_disp_size = 32;
1578 return 1;
1579 }
1580 return 0;
1581 }
1582
1583 if (strcmp (arg, "warn-signed-overflow") == 0)
1584 warn_signed_overflows = TRUE;
1585
1586 else if (strcmp (arg, "warn-unsigned-overflow") == 0)
1587 warn_unsigned_overflows = TRUE;
1588
1589 else if (strcmp (arg, "v850") == 0)
1590 {
1591 machine = 0;
1592 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1593 }
1594 else if (strcmp (arg, "v850e") == 0)
1595 {
1596 machine = bfd_mach_v850e;
1597 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1598 }
1599 else if (strcmp (arg, "v850e1") == 0)
1600 {
1601 machine = bfd_mach_v850e1;
1602 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1603 }
1604 else if (strcmp (arg, "v850e2") == 0)
1605 {
1606 machine = bfd_mach_v850e2;
1607 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1608 }
1609 else if (strcmp (arg, "v850e2v3") == 0)
1610 {
1611 machine = bfd_mach_v850e2v3;
1612 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1613 }
1614 else if (strcmp (arg, "v850e2v4") == 0)
1615 {
1616 machine = bfd_mach_v850e3v5;
1617 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1618 }
1619 else if (strcmp (arg, "v850e3v5") == 0)
1620 {
1621 machine = bfd_mach_v850e3v5;
1622 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1623 }
1624 else if (strcmp (arg, "extension") == 0)
1625 {
1626 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;
1627 }
1628 else if (strcmp (arg, "no-bcond17") == 0)
1629 {
1630 no_bcond17 = 1;
1631 }
1632 else if (strcmp (arg, "no-stld23") == 0)
1633 {
1634 no_stld23 = 1;
1635 }
1636 else if (strcmp (arg, "relax") == 0)
1637 v850_relax = 1;
1638 else if (strcmp (arg, "gcc-abi") == 0)
1639 {
1640 v850_target_arch = bfd_arch_v850;
1641 v850_target_format = "elf32-v850";
1642 }
1643 else if (strcmp (arg, "rh850-abi") == 0)
1644 {
1645 v850_target_arch = bfd_arch_v850_rh850;
1646 v850_target_format = "elf32-v850-rh850";
1647 }
1648 else if (strcmp (arg, "8byte-align") == 0)
1649 v850_e_flags |= EF_RH850_DATA_ALIGN8;
1650 else if (strcmp (arg, "4byte-align") == 0)
1651 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8;
1652 else
1653 return 0;
1654
1655 return 1;
1656 }
1657
1658 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)1659 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1660 {
1661 return 0;
1662 }
1663
1664 char *
md_atof(int type,char * litp,int * sizep)1665 md_atof (int type, char *litp, int *sizep)
1666 {
1667 return ieee_md_atof (type, litp, sizep, FALSE);
1668 }
1669
1670 /* Very gross. */
1671
1672 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,fragS * fragP)1673 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1674 asection *sec,
1675 fragS *fragP)
1676 {
1677 union u
1678 {
1679 bfd_reloc_code_real_type fx_r_type;
1680 char * fr_opcode;
1681 }
1682 opcode_converter;
1683 subseg_change (sec, 0);
1684
1685 opcode_converter.fr_opcode = fragP->fr_opcode;
1686
1687 subseg_change (sec, 0);
1688
1689 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22)
1690 {
1691 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1692 fragP->fr_offset, 1,
1693 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1694 fragP->fr_fix += 4;
1695 }
1696 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1)
1697 {
1698 unsigned char * buffer =
1699 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1700 int loop_reg = (buffer[0] & 0x1f);
1701
1702 /* Add -1.reg. */
1703 md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2);
1704 /* Now create the conditional branch + fixup to the final target. */
1705 /* 0x000107ea = bne LBL(disp17). */
1706 md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4);
1707 fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol,
1708 fragP->fr_offset, 1,
1709 BFD_RELOC_V850_17_PCREL);
1710 fragP->fr_fix += 6;
1711 }
1712 /* In range conditional or unconditional branch. */
1713 else if (fragP->fr_subtype == SUBYPTE_COND_9_22
1714 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
1715 || fragP->fr_subtype == SUBYPTE_COND_9_22_32
1716 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
1717 || fragP->fr_subtype == SUBYPTE_COND_9_17_22
1718 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32
1719 || fragP->fr_subtype == SUBYPTE_SA_9_22
1720 || fragP->fr_subtype == SUBYPTE_SA_9_22_32
1721 || fragP->fr_subtype == SUBYPTE_SA_9_17_22
1722 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32)
1723
1724 {
1725 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
1726 fragP->fr_offset, 1,
1727 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1728 fragP->fr_fix += 2;
1729 }
1730 /* V850e2r-v3 17bit conditional branch. */
1731 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1
1732 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1
1733 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1
1734 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1)
1735 {
1736 unsigned char *buffer =
1737 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1738
1739 buffer[0] &= 0x0f; /* Use condition. */
1740 buffer[0] |= 0xe0;
1741 buffer[1] = 0x07;
1742
1743 /* Now create the unconditional branch + fixup to the final
1744 target. */
1745 md_number_to_chars ((char *) buffer + 2, 0x0001, 2);
1746 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1747 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL);
1748 fragP->fr_fix += 4;
1749 }
1750 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1751 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
1752 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
1753 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
1754 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
1755 {
1756 unsigned char *buffer =
1757 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1758
1759 /* Reverse the condition of the first branch. */
1760 buffer[0] ^= 0x08;
1761 /* Mask off all the displacement bits. */
1762 buffer[0] &= 0x8f;
1763 buffer[1] &= 0x07;
1764 /* Now set the displacement bits so that we branch
1765 around the unconditional branch. */
1766 buffer[0] |= 0x30;
1767
1768 /* Now create the unconditional branch + fixup to the final
1769 target. */
1770 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
1771 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
1772 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1773 fragP->fr_fix += 6;
1774 }
1775 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1776 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2
1777 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3)
1778 {
1779 unsigned char *buffer =
1780 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1781
1782 /* Reverse the condition of the first branch. */
1783 buffer[0] ^= 0x08;
1784 /* Mask off all the displacement bits. */
1785 buffer[0] &= 0x8f;
1786 buffer[1] &= 0x07;
1787 /* Now set the displacement bits so that we branch
1788 around the unconditional branch. */
1789 buffer[0] |= 0x40;
1790
1791 /* Now create the unconditional branch + fixup to the final
1792 target. */
1793 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2);
1794 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1795 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1796 fragP->fr_fix += 8;
1797 }
1798 /* Out of range unconditional branch. Emit a 22bit jump. */
1799 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1
1800 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1)
1801 {
1802 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
1803 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1804 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1805 fragP->fr_fix += 4;
1806 }
1807 /* Out of range unconditional branch. Emit a 32bit jump. */
1808 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2)
1809 {
1810 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2);
1811 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1812 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1813 fragP->fr_fix += 6;
1814 }
1815 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1816 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1
1817 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1
1818 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2
1819 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2)
1820 {
1821 unsigned char *buffer =
1822 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1823
1824 /* bsa .+4 */
1825 buffer[0] &= 0x8f;
1826 buffer[0] |= 0x20;
1827 buffer[1] &= 0x07;
1828
1829 /* br .+6 */
1830 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2);
1831
1832 /* Now create the unconditional branch + fixup to the final
1833 target. */
1834 /* jr SYM */
1835 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4);
1836 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1837 fragP->fr_offset, 1,
1838 BFD_RELOC_V850_22_PCREL);
1839 fragP->fr_fix += 8;
1840 }
1841 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1842 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2
1843 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3)
1844 {
1845 unsigned char *buffer =
1846 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1847
1848 /* bsa .+2 */
1849 buffer[0] &= 0x8f;
1850 buffer[0] |= 0x20;
1851 buffer[1] &= 0x07;
1852
1853 /* br .+8 */
1854 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2);
1855
1856 /* Now create the unconditional branch + fixup to the final
1857 target. */
1858 /* jr SYM */
1859 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2);
1860 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol,
1861 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1862
1863 fragP->fr_fix += 10;
1864 }
1865 else
1866 abort ();
1867 }
1868
1869 valueT
md_section_align(asection * seg,valueT addr)1870 md_section_align (asection *seg, valueT addr)
1871 {
1872 int align = bfd_get_section_alignment (stdoutput, seg);
1873 return ((addr + (1 << align) - 1) & (-1 << align));
1874 }
1875
1876 void
md_begin(void)1877 md_begin (void)
1878 {
1879 char *prev_name = "";
1880 const struct v850_opcode *op;
1881
1882 if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0)
1883 {
1884 if (machine == -1)
1885 machine = bfd_mach_v850e3v5;
1886
1887 if (!processor_mask)
1888 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1889 }
1890 else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0)
1891 {
1892 if (machine == -1)
1893 machine = bfd_mach_v850e3v5;
1894
1895 if (!processor_mask)
1896 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1897 }
1898 else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
1899 {
1900 if (machine == -1)
1901 machine = bfd_mach_v850e2v3;
1902
1903 if (!processor_mask)
1904 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1905 }
1906 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0)
1907 {
1908 if (machine == -1)
1909 machine = bfd_mach_v850e2;
1910
1911 if (!processor_mask)
1912 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1913 }
1914 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
1915 {
1916 if (machine == -1)
1917 machine = bfd_mach_v850e1;
1918
1919 if (!processor_mask)
1920 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1921 }
1922 else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
1923 {
1924 if (machine == -1)
1925 machine = bfd_mach_v850e;
1926
1927 if (!processor_mask)
1928 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1929 }
1930 else if (strncmp (TARGET_CPU, "v850", 4) == 0)
1931 {
1932 if (machine == -1)
1933 machine = 0;
1934
1935 if (!processor_mask)
1936 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1937 }
1938 else
1939 /* xgettext:c-format */
1940 as_bad (_("Unable to determine default target processor from string: %s"),
1941 TARGET_CPU);
1942
1943 v850_hash = hash_new ();
1944
1945 /* Insert unique names into hash table. The V850 instruction set
1946 has many identical opcode names that have different opcodes based
1947 on the operands. This hash table then provides a quick index to
1948 the first opcode with a particular name in the opcode table. */
1949 op = v850_opcodes;
1950 while (op->name)
1951 {
1952 if (strcmp (prev_name, op->name))
1953 {
1954 prev_name = (char *) op->name;
1955 hash_insert (v850_hash, op->name, (char *) op);
1956 }
1957 op++;
1958 }
1959
1960 v850_seg_table[BSS_SECTION].s = bss_section;
1961 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
1962 bfd_set_private_flags (stdoutput, v850_e_flags);
1963 }
1964
1965
1966 static bfd_reloc_code_real_type
handle_hi016(const struct v850_operand * operand,const char ** errmsg)1967 handle_hi016 (const struct v850_operand *operand, const char **errmsg)
1968 {
1969 if (operand == NULL)
1970 return BFD_RELOC_HI16;
1971
1972 if (operand->default_reloc == BFD_RELOC_HI16)
1973 return BFD_RELOC_HI16;
1974
1975 if (operand->default_reloc == BFD_RELOC_HI16_S)
1976 return BFD_RELOC_HI16;
1977
1978 if (operand->default_reloc == BFD_RELOC_16)
1979 return BFD_RELOC_HI16;
1980
1981 *errmsg = _("hi0() relocation used on an instruction which does "
1982 "not support it");
1983 return BFD_RELOC_64; /* Used to indicate an error condition. */
1984 }
1985
1986 static bfd_reloc_code_real_type
handle_hi16(const struct v850_operand * operand,const char ** errmsg)1987 handle_hi16 (const struct v850_operand *operand, const char **errmsg)
1988 {
1989 if (operand == NULL)
1990 return BFD_RELOC_HI16_S;
1991
1992 if (operand->default_reloc == BFD_RELOC_HI16_S)
1993 return BFD_RELOC_HI16_S;
1994
1995 if (operand->default_reloc == BFD_RELOC_HI16)
1996 return BFD_RELOC_HI16_S;
1997
1998 if (operand->default_reloc == BFD_RELOC_16)
1999 return BFD_RELOC_HI16_S;
2000
2001 *errmsg = _("hi() relocation used on an instruction which does "
2002 "not support it");
2003 return BFD_RELOC_64; /* Used to indicate an error condition. */
2004 }
2005
2006 static bfd_reloc_code_real_type
handle_lo16(const struct v850_operand * operand,const char ** errmsg)2007 handle_lo16 (const struct v850_operand *operand, const char **errmsg)
2008 {
2009 if (operand == NULL)
2010 return BFD_RELOC_LO16;
2011
2012 if (operand->default_reloc == BFD_RELOC_LO16)
2013 return BFD_RELOC_LO16;
2014
2015 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2016 return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
2017
2018 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2019 return BFD_RELOC_V850_LO16_S1;
2020
2021 if (operand->default_reloc == BFD_RELOC_16)
2022 return BFD_RELOC_LO16;
2023
2024 *errmsg = _("lo() relocation used on an instruction which does "
2025 "not support it");
2026 return BFD_RELOC_64; /* Used to indicate an error condition. */
2027 }
2028
2029 static bfd_reloc_code_real_type
handle_ctoff(const struct v850_operand * operand,const char ** errmsg)2030 handle_ctoff (const struct v850_operand *operand, const char **errmsg)
2031 {
2032 if (v850_target_arch == bfd_arch_v850_rh850)
2033 {
2034 *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead");
2035 return BFD_RELOC_64; /* Used to indicate an error condition. */
2036 }
2037
2038 if (operand == NULL)
2039 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
2040
2041 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET)
2042 return operand->default_reloc;
2043
2044 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2045 return BFD_RELOC_V850_CALLT_15_16_OFFSET;
2046
2047 if (operand->default_reloc == BFD_RELOC_16)
2048 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
2049
2050 *errmsg = _("ctoff() relocation used on an instruction which does not support it");
2051 return BFD_RELOC_64; /* Used to indicate an error condition. */
2052 }
2053
2054 static bfd_reloc_code_real_type
handle_sdaoff(const struct v850_operand * operand,const char ** errmsg)2055 handle_sdaoff (const struct v850_operand *operand, const char **errmsg)
2056 {
2057 if (operand == NULL)
2058 return BFD_RELOC_V850_SDA_16_16_OFFSET;
2059
2060 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2061 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET;
2062
2063 if (operand->default_reloc == BFD_RELOC_16)
2064 return BFD_RELOC_V850_SDA_16_16_OFFSET;
2065
2066 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2067 return BFD_RELOC_V850_SDA_15_16_OFFSET;
2068
2069 *errmsg = _("sdaoff() relocation used on an instruction which does not support it");
2070 return BFD_RELOC_64; /* Used to indicate an error condition. */
2071 }
2072
2073 static bfd_reloc_code_real_type
handle_zdaoff(const struct v850_operand * operand,const char ** errmsg)2074 handle_zdaoff (const struct v850_operand *operand, const char **errmsg)
2075 {
2076 if (operand == NULL)
2077 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
2078
2079 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2080 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET;
2081
2082 if (operand->default_reloc == BFD_RELOC_16)
2083 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
2084
2085 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2086 return BFD_RELOC_V850_ZDA_15_16_OFFSET;
2087
2088 *errmsg = _("zdaoff() relocation used on an instruction which does not support it");
2089 return BFD_RELOC_64; /* Used to indicate an error condition. */
2090 }
2091
2092 static bfd_reloc_code_real_type
handle_tdaoff(const struct v850_operand * operand,const char ** errmsg)2093 handle_tdaoff (const struct v850_operand *operand, const char **errmsg)
2094 {
2095 if (operand == NULL)
2096 /* Data item, not an instruction. */
2097 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2098
2099 switch (operand->default_reloc)
2100 {
2101 /* sld.hu, operand: D5-4. */
2102 case BFD_RELOC_V850_TDA_4_5_OFFSET:
2103 /* sld.bu, operand: D4. */
2104 case BFD_RELOC_V850_TDA_4_4_OFFSET:
2105 /* sld.w/sst.w, operand: D8_6. */
2106 case BFD_RELOC_V850_TDA_6_8_OFFSET:
2107 /* sld.h/sst.h, operand: D8_7. */
2108 case BFD_RELOC_V850_TDA_7_8_OFFSET:
2109 /* sld.b/sst.b, operand: D7. */
2110 case BFD_RELOC_V850_TDA_7_7_OFFSET:
2111 return operand->default_reloc;
2112 default:
2113 break;
2114 }
2115
2116 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16)
2117 /* set1 & chums, operands: D16. */
2118 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2119
2120 *errmsg = _("tdaoff() relocation used on an instruction which does not support it");
2121 /* Used to indicate an error condition. */
2122 return BFD_RELOC_64;
2123 }
2124
2125 /* Warning: The code in this function relies upon the definitions
2126 in the v850_operands[] array (defined in opcodes/v850-opc.c)
2127 matching the hard coded values contained herein. */
2128
2129 static bfd_reloc_code_real_type
v850_reloc_prefix(const struct v850_operand * operand,const char ** errmsg)2130 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
2131 {
2132 bfd_boolean paren_skipped = FALSE;
2133
2134 /* Skip leading opening parenthesis. */
2135 if (*input_line_pointer == '(')
2136 {
2137 ++input_line_pointer;
2138 paren_skipped = TRUE;
2139 }
2140
2141 #define CHECK_(name, reloc) \
2142 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
2143 { \
2144 input_line_pointer += strlen (name); \
2145 return reloc; \
2146 }
2147
2148 CHECK_ ("hi0", handle_hi016(operand, errmsg) );
2149 CHECK_ ("hi", handle_hi16(operand, errmsg) );
2150 CHECK_ ("lo", handle_lo16 (operand, errmsg) );
2151 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg));
2152 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg));
2153 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg));
2154 CHECK_ ("hilo", BFD_RELOC_32);
2155 CHECK_ ("lo23", BFD_RELOC_V850_23);
2156 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) );
2157
2158 /* Restore skipped parenthesis. */
2159 if (paren_skipped)
2160 --input_line_pointer;
2161
2162 return BFD_RELOC_NONE;
2163 }
2164
2165 /* Insert an operand value into an instruction. */
2166
2167 static unsigned long
v850_insert_operand(unsigned long insn,const struct v850_operand * operand,offsetT val,const char ** errmsg)2168 v850_insert_operand (unsigned long insn,
2169 const struct v850_operand *operand,
2170 offsetT val,
2171 const char **errmsg)
2172 {
2173 if (operand->insert)
2174 {
2175 const char *message = NULL;
2176
2177 insn = operand->insert (insn, val, &message);
2178 if (message != NULL)
2179 {
2180 if ((operand->flags & V850_OPERAND_SIGNED)
2181 && ! warn_signed_overflows
2182 && v850_msg_is_out_of_range (message))
2183 {
2184 /* Skip warning... */
2185 }
2186 else if ((operand->flags & V850_OPERAND_SIGNED) == 0
2187 && ! warn_unsigned_overflows
2188 && v850_msg_is_out_of_range (message))
2189 {
2190 /* Skip warning... */
2191 }
2192 else
2193 {
2194 if (errmsg != NULL)
2195 *errmsg = message;
2196 }
2197 }
2198 }
2199 else if (operand->bits == -1
2200 || operand->flags & V850E_IMMEDIATE16
2201 || operand->flags & V850E_IMMEDIATE23
2202 || operand->flags & V850E_IMMEDIATE32)
2203 {
2204 abort ();
2205 }
2206 else
2207 {
2208 if (operand->bits < 32)
2209 {
2210 long min, max;
2211
2212 if ((operand->flags & V850_OPERAND_SIGNED) != 0)
2213 {
2214 if (! warn_signed_overflows)
2215 max = (1 << operand->bits) - 1;
2216 else
2217 max = (1 << (operand->bits - 1)) - 1;
2218
2219 min = -(1 << (operand->bits - 1));
2220 }
2221 else
2222 {
2223 max = (1 << operand->bits) - 1;
2224
2225 if (! warn_unsigned_overflows)
2226 min = -(1 << (operand->bits - 1));
2227 else
2228 min = 0;
2229 }
2230
2231 /* Some people write constants with the sign extension done by
2232 hand but only up to 32 bits. This shouldn't really be valid,
2233 but, to permit this code to assemble on a 64-bit host, we
2234 sign extend the 32-bit value to 64 bits if so doing makes the
2235 value valid. */
2236 if (val > max
2237 && (offsetT) (val - 0x80000000 - 0x80000000) >= min
2238 && (offsetT) (val - 0x80000000 - 0x80000000) <= max)
2239 val = val - 0x80000000 - 0x80000000;
2240
2241 /* Similarly, people write expressions like ~(1<<15), and expect
2242 this to be OK for a 32-bit unsigned value. */
2243 else if (val < min
2244 && (offsetT) (val + 0x80000000 + 0x80000000) >= min
2245 && (offsetT) (val + 0x80000000 + 0x80000000) <= max)
2246 val = val + 0x80000000 + 0x80000000;
2247
2248 else if (val < (offsetT) min || val > (offsetT) max)
2249 {
2250 static char buf [128];
2251
2252 /* Restore min and mix to expected values for decimal ranges. */
2253 if ((operand->flags & V850_OPERAND_SIGNED)
2254 && ! warn_signed_overflows)
2255 max = (1 << (operand->bits - 1)) - 1;
2256
2257 if (! (operand->flags & V850_OPERAND_SIGNED)
2258 && ! warn_unsigned_overflows)
2259 min = 0;
2260
2261 sprintf (buf, _("operand out of range (%d is not between %d and %d)"),
2262 (int) val, (int) min, (int) max);
2263 *errmsg = buf;
2264 }
2265
2266 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
2267 }
2268 else
2269 {
2270 insn |= (((long) val) << operand->shift);
2271 }
2272 }
2273
2274 return insn;
2275 }
2276
2277 static char copy_of_instruction[128];
2278
2279 void
md_assemble(char * str)2280 md_assemble (char *str)
2281 {
2282 char *s;
2283 char *start_of_operands;
2284 struct v850_opcode *opcode;
2285 struct v850_opcode *next_opcode;
2286 const unsigned char *opindex_ptr;
2287 int next_opindex;
2288 int relaxable = 0;
2289 unsigned long insn;
2290 unsigned long insn_size;
2291 char *f = NULL;
2292 int i;
2293 int match;
2294 bfd_boolean extra_data_after_insn = FALSE;
2295 unsigned extra_data_len = 0;
2296 unsigned long extra_data = 0;
2297 char *saved_input_line_pointer;
2298 char most_match_errmsg[1024];
2299 int most_match_count = -1;
2300
2301 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1);
2302 most_match_errmsg[0] = 0;
2303
2304 /* Get the opcode. */
2305 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
2306 continue;
2307
2308 if (*s != '\0')
2309 *s++ = '\0';
2310
2311 /* Find the first opcode with the proper name. */
2312 opcode = (struct v850_opcode *) hash_find (v850_hash, str);
2313 if (opcode == NULL)
2314 {
2315 /* xgettext:c-format */
2316 as_bad (_("Unrecognized opcode: `%s'"), str);
2317 ignore_rest_of_line ();
2318 return;
2319 }
2320
2321 str = s;
2322 while (ISSPACE (*str))
2323 ++str;
2324
2325 start_of_operands = str;
2326
2327 saved_input_line_pointer = input_line_pointer;
2328
2329 for (;;)
2330 {
2331 const char *errmsg = NULL;
2332 const char *warningmsg = NULL;
2333
2334 match = 0;
2335 opindex_ptr = opcode->operands;
2336
2337 if (no_stld23)
2338 {
2339 if ((strncmp (opcode->name, "st.", 3) == 0
2340 && v850_operands[opcode->operands[1]].bits == 23)
2341 || (strncmp (opcode->name, "ld.", 3) == 0
2342 && v850_operands[opcode->operands[0]].bits == 23))
2343 {
2344 errmsg = _("st/ld offset 23 instruction was disabled .");
2345 goto error;
2346 }
2347 }
2348
2349 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0
2350 || (((opcode->processors & ~PROCESSOR_MASK) != 0)
2351 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0)))
2352 {
2353 errmsg = _("Target processor does not support this instruction.");
2354 goto error;
2355 }
2356
2357 relaxable = 0;
2358 fc = 0;
2359 next_opindex = 0;
2360 insn = opcode->opcode;
2361 extra_data_len = 0;
2362 extra_data_after_insn = FALSE;
2363
2364 input_line_pointer = str = start_of_operands;
2365
2366 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
2367 {
2368 const struct v850_operand *operand;
2369 char *hold;
2370 expressionS ex;
2371 bfd_reloc_code_real_type reloc;
2372
2373 if (next_opindex == 0)
2374 operand = &v850_operands[*opindex_ptr];
2375 else
2376 {
2377 operand = &v850_operands[next_opindex];
2378 next_opindex = 0;
2379 }
2380
2381 errmsg = NULL;
2382
2383 while (*str == ' ')
2384 ++str;
2385
2386 if (operand->flags & V850_OPERAND_BANG
2387 && *str == '!')
2388 ++str;
2389 else if (operand->flags & V850_OPERAND_PERCENT
2390 && *str == '%')
2391 ++str;
2392
2393 if (*str == ',' || *str == '[' || *str == ']')
2394 ++str;
2395
2396 while (*str == ' ')
2397 ++str;
2398
2399 if ( (strcmp (opcode->name, "pushsp") == 0
2400 || strcmp (opcode->name, "popsp") == 0
2401 || strcmp (opcode->name, "dbpush") == 0)
2402 && (*str == '-'))
2403 ++str;
2404
2405 if (operand->flags & V850_OPERAND_RELAX)
2406 relaxable = 1;
2407
2408 /* Gather the operand. */
2409 hold = input_line_pointer;
2410 input_line_pointer = str;
2411
2412 /* lo(), hi(), hi0(), etc... */
2413 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE)
2414 {
2415 /* This is a fake reloc, used to indicate an error condition. */
2416 if (reloc == BFD_RELOC_64)
2417 {
2418 /* match = 1; */
2419 goto error;
2420 }
2421
2422 expression (&ex);
2423
2424 if (ex.X_op == O_constant)
2425 {
2426 switch (reloc)
2427 {
2428 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
2429 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
2430 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
2431 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2432 and the like. */
2433 /* Fall through. */
2434
2435 case BFD_RELOC_LO16:
2436 case BFD_RELOC_V850_LO16_S1:
2437 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
2438 {
2439 /* Truncate, then sign extend the value. */
2440 ex.X_add_number = SEXT16 (ex.X_add_number);
2441 break;
2442 }
2443
2444 case BFD_RELOC_HI16:
2445 {
2446 /* Truncate, then sign extend the value. */
2447 ex.X_add_number = SEXT16 (ex.X_add_number >> 16);
2448 break;
2449 }
2450
2451 case BFD_RELOC_HI16_S:
2452 {
2453 /* Truncate, then sign extend the value. */
2454 int temp = (ex.X_add_number >> 16) & 0xffff;
2455
2456 temp += (ex.X_add_number >> 15) & 1;
2457
2458 ex.X_add_number = SEXT16 (temp);
2459 break;
2460 }
2461
2462 case BFD_RELOC_V850_23:
2463 if ((operand->flags & V850E_IMMEDIATE23) == 0)
2464 {
2465 errmsg = _("immediate operand is too large");
2466 goto error;
2467 }
2468 break;
2469
2470 case BFD_RELOC_32:
2471 case BFD_RELOC_V850_32_ABS:
2472 case BFD_RELOC_V850_32_PCREL:
2473 if ((operand->flags & V850E_IMMEDIATE32) == 0)
2474 {
2475 errmsg = _("immediate operand is too large");
2476 goto error;
2477 }
2478
2479 break;
2480
2481 default:
2482 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc);
2483 break;
2484 }
2485
2486 if (operand->flags & V850E_IMMEDIATE32)
2487 {
2488 extra_data_after_insn = TRUE;
2489 extra_data_len = 4;
2490 extra_data = 0;
2491 }
2492 else if (operand->flags & V850E_IMMEDIATE23)
2493 {
2494 if (reloc != BFD_RELOC_V850_23)
2495 {
2496 errmsg = _("immediate operand is too large");
2497 goto error;
2498 }
2499 extra_data_after_insn = TRUE;
2500 extra_data_len = 2;
2501 extra_data = 0;
2502 }
2503 else if ((operand->flags & V850E_IMMEDIATE16)
2504 || (operand->flags & V850E_IMMEDIATE16HI))
2505 {
2506 if (operand->flags & V850E_IMMEDIATE16HI
2507 && reloc != BFD_RELOC_HI16
2508 && reloc != BFD_RELOC_HI16_S)
2509 {
2510 errmsg = _("immediate operand is too large");
2511 goto error;
2512 }
2513 else if (operand->flags & V850E_IMMEDIATE16
2514 && reloc != BFD_RELOC_LO16)
2515 {
2516 errmsg = _("immediate operand is too large");
2517 goto error;
2518 }
2519
2520 extra_data_after_insn = TRUE;
2521 extra_data_len = 2;
2522 extra_data = 0;
2523 }
2524
2525 if (fc > MAX_INSN_FIXUPS)
2526 as_fatal (_("too many fixups"));
2527
2528 fixups[fc].exp = ex;
2529 fixups[fc].opindex = *opindex_ptr;
2530 fixups[fc].reloc = reloc;
2531 fc++;
2532 }
2533 else /* ex.X_op != O_constant. */
2534 {
2535 if ((reloc == BFD_RELOC_32
2536 || reloc == BFD_RELOC_V850_32_ABS
2537 || reloc == BFD_RELOC_V850_32_PCREL)
2538 && operand->bits < 32)
2539 {
2540 errmsg = _("immediate operand is too large");
2541 goto error;
2542 }
2543 else if (reloc == BFD_RELOC_V850_23
2544 && (operand->flags & V850E_IMMEDIATE23) == 0)
2545 {
2546 errmsg = _("immediate operand is too large");
2547 goto error;
2548 }
2549 else if ((reloc == BFD_RELOC_HI16
2550 || reloc == BFD_RELOC_HI16_S)
2551 && operand->bits < 16)
2552 {
2553 errmsg = _("immediate operand is too large");
2554 goto error;
2555 }
2556
2557 if (operand->flags & V850E_IMMEDIATE32)
2558 {
2559 extra_data_after_insn = TRUE;
2560 extra_data_len = 4;
2561 extra_data = 0;
2562 }
2563 else if (operand->flags & V850E_IMMEDIATE23)
2564 {
2565 if (reloc != BFD_RELOC_V850_23)
2566 {
2567 errmsg = _("immediate operand is too large");
2568 goto error;
2569 }
2570 extra_data_after_insn = TRUE;
2571 extra_data_len = 2;
2572 extra_data = 0;
2573 }
2574 else if ((operand->flags & V850E_IMMEDIATE16)
2575 || (operand->flags & V850E_IMMEDIATE16HI))
2576 {
2577 if (operand->flags & V850E_IMMEDIATE16HI
2578 && reloc != BFD_RELOC_HI16
2579 && reloc != BFD_RELOC_HI16_S)
2580 {
2581 errmsg = _("immediate operand is too large");
2582 goto error;
2583 }
2584 else if (operand->flags & V850E_IMMEDIATE16
2585 && reloc != BFD_RELOC_LO16)
2586 {
2587 errmsg = _("immediate operand is too large");
2588 goto error;
2589 }
2590
2591 extra_data_after_insn = TRUE;
2592 extra_data_len = 2;
2593 extra_data = 0;
2594 }
2595
2596 if (fc > MAX_INSN_FIXUPS)
2597 as_fatal (_("too many fixups"));
2598
2599 fixups[fc].exp = ex;
2600 fixups[fc].opindex = *opindex_ptr;
2601 fixups[fc].reloc = reloc;
2602 fc++;
2603 }
2604 }
2605 else if (operand->flags & V850E_IMMEDIATE16
2606 || operand->flags & V850E_IMMEDIATE16HI)
2607 {
2608 expression (&ex);
2609
2610 switch (ex.X_op)
2611 {
2612 case O_constant:
2613 if (operand->flags & V850E_IMMEDIATE16HI)
2614 {
2615 if (ex.X_add_number & 0xffff)
2616 {
2617 errmsg = _("constant too big to fit into instruction");
2618 goto error;
2619 }
2620
2621 ex.X_add_number >>= 16;
2622 }
2623 if (operand->flags & V850E_IMMEDIATE16)
2624 {
2625 if ((ex.X_add_number & 0xffff8000)
2626 && ((ex.X_add_number & 0xffff8000) != 0xffff8000))
2627 {
2628 errmsg = _("constant too big to fit into instruction");
2629 goto error;
2630 }
2631 }
2632 break;
2633
2634 case O_illegal:
2635 errmsg = _("illegal operand");
2636 goto error;
2637
2638 case O_absent:
2639 errmsg = _("missing operand");
2640 goto error;
2641
2642 default:
2643 if (fc >= MAX_INSN_FIXUPS)
2644 as_fatal (_("too many fixups"));
2645
2646 fixups[fc].exp = ex;
2647 fixups[fc].opindex = *opindex_ptr;
2648 fixups[fc].reloc = operand->default_reloc;
2649 ++fc;
2650
2651 ex.X_add_number = 0;
2652 break;
2653 }
2654
2655 extra_data_after_insn = TRUE;
2656 extra_data_len = 2;
2657 extra_data = ex.X_add_number;
2658 }
2659 else if (operand->flags & V850E_IMMEDIATE23)
2660 {
2661 expression (&ex);
2662
2663 switch (ex.X_op)
2664 {
2665 case O_constant:
2666 break;
2667
2668 case O_illegal:
2669 errmsg = _("illegal operand");
2670 goto error;
2671
2672 case O_absent:
2673 errmsg = _("missing operand");
2674 goto error;
2675
2676 default:
2677 break;
2678 }
2679
2680 if (fc >= MAX_INSN_FIXUPS)
2681 as_fatal (_("too many fixups"));
2682
2683 fixups[fc].exp = ex;
2684 fixups[fc].opindex = *opindex_ptr;
2685 fixups[fc].reloc = operand->default_reloc;
2686 ++fc;
2687
2688 extra_data_after_insn = TRUE;
2689 extra_data_len = 2;
2690 extra_data = 0;
2691 }
2692 else if (operand->flags & V850E_IMMEDIATE32)
2693 {
2694 expression (&ex);
2695
2696 switch (ex.X_op)
2697 {
2698 case O_constant:
2699 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS
2700 || operand->default_reloc == BFD_RELOC_V850_32_PCREL)
2701 && (ex.X_add_number & 1))
2702 {
2703 errmsg = _("odd number cannot be used here");
2704 goto error;
2705 }
2706 break;
2707
2708 case O_illegal:
2709 errmsg = _("illegal operand");
2710 goto error;
2711
2712 case O_absent:
2713 errmsg = _("missing operand");
2714 goto error;
2715
2716 default:
2717 if (fc >= MAX_INSN_FIXUPS)
2718 as_fatal (_("too many fixups"));
2719
2720 fixups[fc].exp = ex;
2721 fixups[fc].opindex = *opindex_ptr;
2722 fixups[fc].reloc = operand->default_reloc;
2723 ++fc;
2724
2725 ex.X_add_number = 0;
2726 break;
2727 }
2728
2729 extra_data_after_insn = TRUE;
2730 extra_data_len = 4;
2731 extra_data = ex.X_add_number;
2732 }
2733 else if (operand->flags & V850E_OPERAND_REG_LIST)
2734 {
2735 errmsg = parse_register_list (&insn, operand);
2736
2737 if (errmsg)
2738 goto error;
2739 }
2740 else
2741 {
2742 errmsg = NULL;
2743
2744 if ((operand->flags & V850_OPERAND_REG) != 0)
2745 {
2746 if (!register_name (&ex))
2747 {
2748 errmsg = _("invalid register name");
2749 }
2750
2751 if ((operand->flags & V850_NOT_R0)
2752 && ex.X_add_number == 0)
2753 {
2754 errmsg = _("register r0 cannot be used here");
2755 }
2756
2757 if (operand->flags & V850_REG_EVEN)
2758 {
2759 if (ex.X_add_number % 2)
2760 errmsg = _("odd register cannot be used here");
2761 ex.X_add_number = ex.X_add_number / 2;
2762 }
2763
2764 }
2765 else if ((operand->flags & V850_OPERAND_SRG) != 0)
2766 {
2767 if (!system_register_name (&ex, TRUE))
2768 {
2769 errmsg = _("invalid system register name");
2770 }
2771 }
2772 else if ((operand->flags & V850_OPERAND_EP) != 0)
2773 {
2774 char *start = input_line_pointer;
2775 char c = get_symbol_end ();
2776
2777 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
2778 {
2779 /* Put things back the way we found them. */
2780 *input_line_pointer = c;
2781 input_line_pointer = start;
2782 errmsg = _("expected EP register");
2783 goto error;
2784 }
2785
2786 *input_line_pointer = c;
2787 str = input_line_pointer;
2788 input_line_pointer = hold;
2789
2790 while (*str == ' ' || *str == ','
2791 || *str == '[' || *str == ']')
2792 ++str;
2793 continue;
2794 }
2795 else if ((operand->flags & V850_OPERAND_CC) != 0)
2796 {
2797 if (!cc_name (&ex, TRUE))
2798 {
2799 errmsg = _("invalid condition code name");
2800 }
2801
2802 if ((operand->flags & V850_NOT_SA)
2803 && ex.X_add_number == COND_SA_NUM)
2804 {
2805 errmsg = _("condition sa cannot be used here");
2806 }
2807 }
2808 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
2809 {
2810 if (!float_cc_name (&ex, TRUE))
2811 {
2812 errmsg = _("invalid condition code name");
2813 }
2814 }
2815 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
2816 {
2817 if (!cacheop_name (&ex, TRUE))
2818 errmsg = _("invalid cache oparation name");
2819 }
2820 else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
2821 {
2822 if (!prefop_name (&ex, TRUE))
2823 errmsg = _("invalid pref oparation name");
2824 }
2825 else if ((operand->flags & V850_OPERAND_VREG) != 0)
2826 {
2827 if (!vector_register_name (&ex))
2828 errmsg = _("invalid vector register name");
2829 }
2830 else if ((register_name (&ex)
2831 && (operand->flags & V850_OPERAND_REG) == 0))
2832 {
2833 char c;
2834 int exists = 0;
2835
2836 /* It is possible that an alias has been defined that
2837 matches a register name. For example the code may
2838 include a ".set ZERO, 0" directive, which matches
2839 the register name "zero". Attempt to reparse the
2840 field as an expression, and only complain if we
2841 cannot generate a constant. */
2842
2843 input_line_pointer = str;
2844
2845 c = get_symbol_end ();
2846
2847 if (symbol_find (str) != NULL)
2848 exists = 1;
2849
2850 *input_line_pointer = c;
2851 input_line_pointer = str;
2852
2853 expression (&ex);
2854
2855 if (ex.X_op != O_constant)
2856 {
2857 /* If this register is actually occurring too early on
2858 the parsing of the instruction, (because another
2859 field is missing) then report this. */
2860 if (opindex_ptr[1] != 0
2861 && ((v850_operands[opindex_ptr[1]].flags
2862 & V850_OPERAND_REG)
2863 ||(v850_operands[opindex_ptr[1]].flags
2864 & V850_OPERAND_VREG)))
2865 errmsg = _("syntax error: value is missing before the register name");
2866 else
2867 errmsg = _("syntax error: register not expected");
2868
2869 /* If we created a symbol in the process of this
2870 test then delete it now, so that it will not
2871 be output with the real symbols... */
2872 if (exists == 0
2873 && ex.X_op == O_symbol)
2874 symbol_remove (ex.X_add_symbol,
2875 &symbol_rootP, &symbol_lastP);
2876 }
2877 }
2878 else if (system_register_name (&ex, FALSE)
2879 && (operand->flags & V850_OPERAND_SRG) == 0)
2880 {
2881 errmsg = _("syntax error: system register not expected");
2882 }
2883 else if (cc_name (&ex, FALSE)
2884 && (operand->flags & V850_OPERAND_CC) == 0)
2885 {
2886 errmsg = _("syntax error: condition code not expected");
2887 }
2888 else if (float_cc_name (&ex, FALSE)
2889 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
2890 {
2891 errmsg = _("syntax error: condition code not expected");
2892 }
2893 else if (vector_register_name (&ex)
2894 && (operand->flags & V850_OPERAND_VREG) == 0)
2895 {
2896 errmsg = _("syntax error: vector register not expected");
2897 }
2898 else
2899 {
2900 expression (&ex);
2901
2902 if ((operand->flags & V850_NOT_IMM0)
2903 && ex.X_op == O_constant
2904 && ex.X_add_number == 0)
2905 {
2906 errmsg = _("immediate 0 cannot be used here");
2907 }
2908
2909 /* Special case:
2910 If we are assembling a MOV/JARL/JR instruction and the immediate
2911 value does not fit into the bits available then create a
2912 fake error so that the next MOV/JARL/JR instruction will be
2913 selected. This one has a 32 bit immediate field. */
2914
2915 if ((strcmp (opcode->name, "mov") == 0
2916 || strcmp (opcode->name, "jarl") == 0
2917 || strcmp (opcode->name, "jr") == 0)
2918 && ex.X_op == O_constant
2919 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2920 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2921 {
2922 errmsg = _("immediate operand is too large");
2923 }
2924
2925 if ((strcmp (opcode->name, "jarl") == 0
2926 || strcmp (opcode->name, "jr") == 0)
2927 && ex.X_op != O_constant
2928 && operand->bits != default_disp_size)
2929 {
2930 errmsg = _("immediate operand is not match");
2931 }
2932
2933 /* Special case2 :
2934 If we are assembling a ld/st instruction and the immediate
2935 value does not fit into the bits available then create a
2936 fake error so that the next ld/st instruction will be
2937 selected. */
2938 if ( ( (strncmp (opcode->name, "st.", 3) == 0)
2939 || (strncmp (opcode->name, "ld.", 3) == 0))
2940 && ex.X_op == O_constant
2941 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2942 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2943 errmsg = _("displacement is too large");
2944 }
2945
2946 if (errmsg)
2947 goto error;
2948
2949 switch (ex.X_op)
2950 {
2951 case O_illegal:
2952 errmsg = _("illegal operand");
2953 goto error;
2954 case O_absent:
2955 errmsg = _("missing operand");
2956 goto error;
2957 case O_register:
2958 if ((operand->flags
2959 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0)
2960 {
2961 errmsg = _("invalid operand");
2962 goto error;
2963 }
2964
2965 insn = v850_insert_operand (insn, operand,
2966 ex.X_add_number,
2967 &warningmsg);
2968
2969 break;
2970
2971 case O_constant:
2972 insn = v850_insert_operand (insn, operand, ex.X_add_number,
2973 &warningmsg);
2974 break;
2975
2976 default:
2977 /* We need to generate a fixup for this expression. */
2978 if (fc >= MAX_INSN_FIXUPS)
2979 as_fatal (_("too many fixups"));
2980
2981 fixups[fc].exp = ex;
2982 fixups[fc].opindex = *opindex_ptr;
2983 fixups[fc].reloc = BFD_RELOC_NONE;
2984 ++fc;
2985 break;
2986 }
2987 }
2988
2989 str = input_line_pointer;
2990 input_line_pointer = hold;
2991
2992 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']'
2993 || *str == ')')
2994 ++str;
2995 }
2996
2997 while (ISSPACE (*str))
2998 ++str;
2999
3000 if (*str == '\0')
3001 match = 1;
3002
3003 error:
3004 if (match == 0)
3005 {
3006 if ((opindex_ptr - opcode->operands) >= most_match_count)
3007 {
3008 most_match_count = opindex_ptr - opcode->operands;
3009 if (errmsg != NULL)
3010 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1);
3011 }
3012
3013 next_opcode = opcode + 1;
3014 if (next_opcode->name != NULL
3015 && strcmp (next_opcode->name, opcode->name) == 0)
3016 {
3017 opcode = next_opcode;
3018
3019 /* Skip versions that are not supported by the target
3020 processor. */
3021 if ((opcode->processors & processor_mask) == 0)
3022 goto error;
3023
3024 continue;
3025 }
3026
3027 if (most_match_errmsg[0] == 0)
3028 /* xgettext:c-format. */
3029 as_bad (_("junk at end of line: `%s'"), str);
3030 else
3031 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg);
3032
3033 if (*input_line_pointer == ']')
3034 ++input_line_pointer;
3035
3036 ignore_rest_of_line ();
3037 input_line_pointer = saved_input_line_pointer;
3038 return;
3039 }
3040
3041 if (warningmsg != NULL)
3042 as_warn ("%s", warningmsg);
3043 break;
3044 }
3045
3046 input_line_pointer = str;
3047
3048 /* Tie dwarf2 debug info to the address at the start of the insn.
3049 We can't do this after the insn has been output as the current
3050 frag may have been closed off. eg. by frag_var. */
3051 dwarf2_emit_insn (0);
3052
3053 /* Write out the instruction. */
3054
3055 if (relaxable && fc > 0)
3056 {
3057 insn_size = 2;
3058 fc = 0;
3059
3060 if (strcmp (opcode->name, "loop") == 0)
3061 {
3062 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22)
3063 {
3064 insn_size = 4;
3065 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22,
3066 fixups[0].exp.X_add_symbol,
3067 fixups[0].exp.X_add_number,
3068 (char *)(size_t) fixups[0].opindex);
3069 md_number_to_chars (f, insn, insn_size);
3070 md_number_to_chars (f+4, 0, 4);
3071 }
3072 else
3073 {
3074 as_bad (_("loop: 32-bit displacement not supported"));
3075 }
3076 }
3077 else if (strcmp (opcode->name, "br") == 0
3078 || strcmp (opcode->name, "jbr") == 0)
3079 {
3080 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
3081 {
3082 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
3083 fixups[0].exp.X_add_symbol,
3084 fixups[0].exp.X_add_number,
3085 (char *)(size_t) fixups[0].opindex);
3086 md_number_to_chars (f, insn, insn_size);
3087 md_number_to_chars (f + 2, 0, 2);
3088 }
3089 else
3090 {
3091 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32,
3092 fixups[0].exp.X_add_symbol,
3093 fixups[0].exp.X_add_number,
3094 (char *)(size_t) fixups[0].opindex);
3095 md_number_to_chars (f, insn, insn_size);
3096 md_number_to_chars (f + 2, 0, 4);
3097 }
3098 }
3099 else /* b<cond>, j<cond>. */
3100 {
3101 if (default_disp_size == 22
3102 || (processor_mask & PROCESSOR_V850E2_UP) == 0)
3103 {
3104 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
3105 {
3106 if (strcmp (opcode->name, "bsa") == 0)
3107 {
3108 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22,
3109 fixups[0].exp.X_add_symbol,
3110 fixups[0].exp.X_add_number,
3111 (char *)(size_t) fixups[0].opindex);
3112 md_number_to_chars (f, insn, insn_size);
3113 md_number_to_chars (f + 2, 0, 6);
3114 }
3115 else
3116 {
3117 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22,
3118 fixups[0].exp.X_add_symbol,
3119 fixups[0].exp.X_add_number,
3120 (char *)(size_t) fixups[0].opindex);
3121 md_number_to_chars (f, insn, insn_size);
3122 md_number_to_chars (f + 2, 0, 4);
3123 }
3124 }
3125 else
3126 {
3127 if (strcmp (opcode->name, "bsa") == 0)
3128 {
3129 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22,
3130 fixups[0].exp.X_add_symbol,
3131 fixups[0].exp.X_add_number,
3132 (char *)(size_t) fixups[0].opindex);
3133 md_number_to_chars (f, insn, insn_size);
3134 md_number_to_chars (f + 2, 0, 6);
3135 }
3136 else
3137 {
3138 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22,
3139 fixups[0].exp.X_add_symbol,
3140 fixups[0].exp.X_add_number,
3141 (char *)(size_t) fixups[0].opindex);
3142 md_number_to_chars (f, insn, insn_size);
3143 md_number_to_chars (f + 2, 0, 4);
3144 }
3145 }
3146 }
3147 else
3148 {
3149 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
3150 {
3151 if (strcmp (opcode->name, "bsa") == 0)
3152 {
3153 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32,
3154 fixups[0].exp.X_add_symbol,
3155 fixups[0].exp.X_add_number,
3156 (char *)(size_t) fixups[0].opindex);
3157 md_number_to_chars (f, insn, insn_size);
3158 md_number_to_chars (f + 2, 0, 8);
3159 }
3160 else
3161 {
3162 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32,
3163 fixups[0].exp.X_add_symbol,
3164 fixups[0].exp.X_add_number,
3165 (char *)(size_t) fixups[0].opindex);
3166 md_number_to_chars (f, insn, insn_size);
3167 md_number_to_chars (f + 2, 0, 6);
3168 }
3169 }
3170 else
3171 {
3172 if (strcmp (opcode->name, "bsa") == 0)
3173 {
3174 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32,
3175 fixups[0].exp.X_add_symbol,
3176 fixups[0].exp.X_add_number,
3177 (char *)(size_t) fixups[0].opindex);
3178 md_number_to_chars (f, insn, insn_size);
3179 md_number_to_chars (f + 2, 0, 8);
3180 }
3181 else
3182 {
3183 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32,
3184 fixups[0].exp.X_add_symbol,
3185 fixups[0].exp.X_add_number,
3186 (char *)(size_t) fixups[0].opindex);
3187 md_number_to_chars (f, insn, insn_size);
3188 md_number_to_chars (f + 2, 0, 6);
3189 }
3190 }
3191 }
3192 }
3193 }
3194 else
3195 {
3196 /* Four byte insns have an opcode with the two high bits on. */
3197 if ((insn & 0x0600) == 0x0600)
3198 insn_size = 4;
3199 else
3200 insn_size = 2;
3201
3202 /* Special case: 32 bit MOV. */
3203 if ((insn & 0xffe0) == 0x0620)
3204 insn_size = 2;
3205
3206 /* Special case: 32 bit JARL,JMP,JR. */
3207 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */
3208 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */
3209 || (insn & 0x1ffff) == 0x2e0) /* JR. */
3210 insn_size = 2;
3211
3212 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len))
3213 {
3214 frag_wane (frag_now);
3215 frag_new (0);
3216 }
3217
3218 f = frag_more (insn_size);
3219 md_number_to_chars (f, insn, insn_size);
3220
3221 if (extra_data_after_insn)
3222 {
3223 f = frag_more (extra_data_len);
3224 md_number_to_chars (f, extra_data, extra_data_len);
3225
3226 extra_data_after_insn = FALSE;
3227 }
3228 }
3229
3230 /* Create any fixups. At this point we do not use a
3231 bfd_reloc_code_real_type, but instead just use the
3232 BFD_RELOC_UNUSED plus the operand index. This lets us easily
3233 handle fixups for any operand type, although that is admittedly
3234 not a very exciting feature. We pick a BFD reloc type in
3235 md_apply_fix. */
3236 for (i = 0; i < fc; i++)
3237 {
3238 const struct v850_operand *operand;
3239 bfd_reloc_code_real_type reloc;
3240
3241 operand = &v850_operands[fixups[i].opindex];
3242
3243 reloc = fixups[i].reloc;
3244
3245 if (reloc != BFD_RELOC_NONE)
3246 {
3247 reloc_howto_type *reloc_howto =
3248 bfd_reloc_type_lookup (stdoutput, reloc);
3249 int size;
3250 int address;
3251 fixS *fixP;
3252
3253 if (!reloc_howto)
3254 abort ();
3255
3256 size = bfd_get_reloc_size (reloc_howto);
3257
3258 /* XXX This will abort on an R_V850_8 reloc -
3259 is this reloc actually used? */
3260 if (size != 2 && size != 4)
3261 abort ();
3262
3263 if (extra_data_len == 0)
3264 {
3265 address = (f - frag_now->fr_literal) + insn_size - size;
3266 }
3267 else
3268 {
3269 address = (f - frag_now->fr_literal) + extra_data_len - size;
3270 }
3271
3272 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL))
3273 {
3274 fixups[i].exp.X_add_number += 2;
3275 }
3276 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3277 {
3278 fixups[i].exp.X_add_number += 2;
3279 address += 2;
3280 }
3281
3282 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
3283 fixP = fix_new_exp (frag_now, address, size,
3284 &fixups[i].exp,
3285 reloc_howto->pc_relative,
3286 reloc);
3287
3288 fixP->tc_fix_data = (void *) operand;
3289
3290 switch (reloc)
3291 {
3292 case BFD_RELOC_LO16:
3293 case BFD_RELOC_V850_LO16_S1:
3294 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3295 case BFD_RELOC_HI16:
3296 case BFD_RELOC_HI16_S:
3297 fixP->fx_no_overflow = 1;
3298 break;
3299 default:
3300 break;
3301 }
3302 }
3303 else
3304 {
3305 gas_assert (f != NULL);
3306 fix_new_exp (frag_now,
3307 f - frag_now->fr_literal, 4,
3308 & fixups[i].exp,
3309 (operand->flags & V850_PCREL) != 0,
3310 (bfd_reloc_code_real_type) (fixups[i].opindex
3311 + (int) BFD_RELOC_UNUSED));
3312 }
3313 }
3314
3315 input_line_pointer = saved_input_line_pointer;
3316 }
3317
3318 /* If while processing a fixup, a reloc really needs to be created
3319 then it is done here. */
3320
3321 arelent *
tc_gen_reloc(asection * seg ATTRIBUTE_UNUSED,fixS * fixp)3322 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
3323 {
3324 arelent *reloc;
3325
3326 reloc = xmalloc (sizeof (arelent));
3327 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3328 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3329 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3330
3331 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
3332 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3333 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL
3334 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP
3335 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN)
3336 reloc->addend = fixp->fx_offset;
3337 else
3338 {
3339 #if 0
3340 if (fixp->fx_r_type == BFD_RELOC_32
3341 && fixp->fx_pcrel)
3342 fixp->fx_r_type = BFD_RELOC_32_PCREL;
3343 #endif
3344
3345 reloc->addend = fixp->fx_addnumber;
3346 }
3347
3348 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3349
3350 if (reloc->howto == NULL)
3351 {
3352 as_bad_where (fixp->fx_file, fixp->fx_line,
3353 /* xgettext:c-format */
3354 _("reloc %d not supported by object file format"),
3355 (int) fixp->fx_r_type);
3356
3357 xfree (reloc);
3358
3359 return NULL;
3360 }
3361
3362 return reloc;
3363 }
3364
3365 void
v850_handle_align(fragS * frag)3366 v850_handle_align (fragS * frag)
3367 {
3368 if (v850_relax
3369 && frag->fr_type == rs_align
3370 && frag->fr_address + frag->fr_fix > 0
3371 && frag->fr_offset > 1
3372 && now_seg != bss_section
3373 && now_seg != v850_seg_table[SBSS_SECTION].s
3374 && now_seg != v850_seg_table[TBSS_SECTION].s
3375 && now_seg != v850_seg_table[ZBSS_SECTION].s)
3376 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0,
3377 BFD_RELOC_V850_ALIGN);
3378 }
3379
3380 /* Return current size of variable part of frag. */
3381
3382 int
md_estimate_size_before_relax(fragS * fragp,asection * seg ATTRIBUTE_UNUSED)3383 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
3384 {
3385 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
3386 abort ();
3387
3388 return md_relax_table[fragp->fr_subtype].rlx_length;
3389 }
3390
3391 long
v850_pcrel_from_section(fixS * fixp,segT section)3392 v850_pcrel_from_section (fixS *fixp, segT section)
3393 {
3394 /* If the symbol is undefined, or in a section other than our own,
3395 or it is weak (in which case it may well be in another section,
3396 then let the linker figure it out. */
3397 if (fixp->fx_addsy != (symbolS *) NULL
3398 && (! S_IS_DEFINED (fixp->fx_addsy)
3399 || S_IS_WEAK (fixp->fx_addsy)
3400 || (S_GET_SEGMENT (fixp->fx_addsy) != section)))
3401 return 0;
3402
3403 return fixp->fx_frag->fr_address + fixp->fx_where;
3404 }
3405
3406 void
md_apply_fix(fixS * fixP,valueT * valueP,segT seg ATTRIBUTE_UNUSED)3407 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
3408 {
3409 valueT value = * valueP;
3410 char *where;
3411
3412 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3413 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3414 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP
3415 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3416 {
3417 fixP->fx_done = 0;
3418 return;
3419 }
3420
3421 if (fixP->fx_addsy == (symbolS *) NULL)
3422 fixP->fx_addnumber = value,
3423 fixP->fx_done = 1;
3424
3425 else if (fixP->fx_pcrel)
3426 fixP->fx_addnumber = fixP->fx_offset;
3427
3428 else
3429 {
3430 value = fixP->fx_offset;
3431 if (fixP->fx_subsy != (symbolS *) NULL)
3432 {
3433 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
3434 value -= S_GET_VALUE (fixP->fx_subsy);
3435 else
3436 /* We don't actually support subtracting a symbol. */
3437 as_bad_where (fixP->fx_file, fixP->fx_line,
3438 _("expression too complex"));
3439 }
3440 fixP->fx_addnumber = value;
3441 }
3442
3443 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
3444 {
3445 int opindex;
3446 const struct v850_operand *operand;
3447 unsigned long insn;
3448 const char *errmsg = NULL;
3449
3450 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
3451 operand = &v850_operands[opindex];
3452
3453 /* Fetch the instruction, insert the fully resolved operand
3454 value, and stuff the instruction back again.
3455
3456 Note the instruction has been stored in little endian
3457 format! */
3458 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3459
3460 if (fixP->fx_size > 2)
3461 insn = bfd_getl32 ((unsigned char *) where);
3462 else
3463 insn = bfd_getl16 ((unsigned char *) where);
3464
3465 /* When inserting loop offets a backwards displacement
3466 is encoded as a positive value. */
3467 if (operand->flags & V850_INVERSE_PCREL)
3468 value = - value;
3469
3470 insn = v850_insert_operand (insn, operand, (offsetT) value,
3471 &errmsg);
3472 if (errmsg)
3473 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg);
3474
3475 if (fixP->fx_size > 2)
3476 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3477 else
3478 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
3479
3480 if (fixP->fx_done)
3481 /* Nothing else to do here. */
3482 return;
3483
3484 /* Determine a BFD reloc value based on the operand information.
3485 We are only prepared to turn a few of the operands into relocs. */
3486
3487 if (operand->default_reloc == BFD_RELOC_NONE)
3488 {
3489 as_bad_where (fixP->fx_file, fixP->fx_line,
3490 _("unresolved expression that must be resolved"));
3491 fixP->fx_done = 1;
3492 return;
3493 }
3494
3495 {
3496 fixP->fx_r_type = operand->default_reloc;
3497 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3498 {
3499 fixP->fx_where += 2;
3500 fixP->fx_size = 2;
3501 fixP->fx_addnumber += 2;
3502 }
3503 }
3504 }
3505 else if (fixP->fx_done)
3506 {
3507 /* We still have to insert the value into memory! */
3508 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3509
3510 if (fixP->tc_fix_data != NULL
3511 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
3512 {
3513 const char * message = NULL;
3514 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
3515 unsigned long insn;
3516
3517 /* The variable "where" currently points at the exact point inside
3518 the insn where we need to insert the value. But we need to
3519 extract the entire insn so we probably need to move "where"
3520 back a few bytes. */
3521
3522 if (fixP->fx_size == 2)
3523 where -= 2;
3524 else if (fixP->fx_size == 1)
3525 where -= 3;
3526
3527 insn = bfd_getl32 ((unsigned char *) where);
3528
3529 /* Use the operand's insertion procedure, if present, in order to
3530 make sure that the value is correctly stored in the insn. */
3531 insn = operand->insert (insn, (offsetT) value, & message);
3532 /* Ignore message even if it is set. */
3533
3534 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3535 }
3536 else
3537 {
3538 switch (fixP->fx_r_type)
3539 {
3540 case BFD_RELOC_V850_32_ABS:
3541 case BFD_RELOC_V850_32_PCREL:
3542 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where);
3543 break;
3544
3545 case BFD_RELOC_32:
3546 bfd_putl32 (value, (unsigned char *) where);
3547 break;
3548
3549 case BFD_RELOC_V850_23:
3550 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7))
3551 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))),
3552 (unsigned char *) where);
3553 break;
3554
3555 case BFD_RELOC_16:
3556 case BFD_RELOC_HI16:
3557 case BFD_RELOC_HI16_S:
3558 case BFD_RELOC_LO16:
3559 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
3560 case BFD_RELOC_V850_SDA_16_16_OFFSET:
3561 case BFD_RELOC_V850_TDA_16_16_OFFSET:
3562 case BFD_RELOC_V850_CALLT_16_16_OFFSET:
3563 bfd_putl16 (value & 0xffff, (unsigned char *) where);
3564 break;
3565
3566 case BFD_RELOC_8:
3567 *where = value & 0xff;
3568 break;
3569
3570 case BFD_RELOC_V850_9_PCREL:
3571 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3)
3572 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where);
3573 break;
3574
3575 case BFD_RELOC_V850_17_PCREL:
3576 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16)
3577 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where);
3578 break;
3579
3580 case BFD_RELOC_V850_16_PCREL:
3581 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001),
3582 (unsigned char *) (where + 2));
3583 break;
3584
3585 case BFD_RELOC_V850_22_PCREL:
3586 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)
3587 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where);
3588 break;
3589
3590 case BFD_RELOC_V850_16_S1:
3591 case BFD_RELOC_V850_LO16_S1:
3592 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
3593 case BFD_RELOC_V850_SDA_15_16_OFFSET:
3594 bfd_putl16 (value & 0xfffe, (unsigned char *) where);
3595 break;
3596
3597 case BFD_RELOC_V850_16_SPLIT_OFFSET:
3598 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3599 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
3600 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET:
3601 bfd_putl32 (((value << 16) & 0xfffe0000)
3602 | ((value << 5) & 0x20)
3603 | (bfd_getl32 (where) & ~0xfffe0020), where);
3604 break;
3605
3606 case BFD_RELOC_V850_TDA_6_8_OFFSET:
3607 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e);
3608 break;
3609
3610 case BFD_RELOC_V850_TDA_7_8_OFFSET:
3611 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f);
3612 break;
3613
3614 case BFD_RELOC_V850_TDA_7_7_OFFSET:
3615 *where = (*where & ~0x7f) | (value & 0x7f);
3616 break;
3617
3618 case BFD_RELOC_V850_TDA_4_5_OFFSET:
3619 *where = (*where & ~0xf) | ((value >> 1) & 0xf);
3620 break;
3621
3622 case BFD_RELOC_V850_TDA_4_4_OFFSET:
3623 *where = (*where & ~0xf) | (value & 0xf);
3624 break;
3625
3626 case BFD_RELOC_V850_CALLT_6_7_OFFSET:
3627 *where = (*where & ~0x3f) | (value & 0x3f);
3628 break;
3629
3630 default:
3631 abort ();
3632 }
3633 }
3634 }
3635 }
3636
3637 /* Parse a cons expression. We have to handle hi(), lo(), etc
3638 on the v850. */
3639
3640 bfd_reloc_code_real_type
parse_cons_expression_v850(expressionS * exp)3641 parse_cons_expression_v850 (expressionS *exp)
3642 {
3643 const char *errmsg;
3644 bfd_reloc_code_real_type r;
3645
3646 /* See if there's a reloc prefix like hi() we have to handle. */
3647 r = v850_reloc_prefix (NULL, &errmsg);
3648
3649 /* Do normal expression parsing. */
3650 expression (exp);
3651 return r;
3652 }
3653
3654 /* Create a fixup for a cons expression. If parse_cons_expression_v850
3655 found a reloc prefix, then we use that reloc, else we choose an
3656 appropriate one based on the size of the expression. */
3657
3658 void
cons_fix_new_v850(fragS * frag,int where,int size,expressionS * exp,bfd_reloc_code_real_type r)3659 cons_fix_new_v850 (fragS *frag,
3660 int where,
3661 int size,
3662 expressionS *exp,
3663 bfd_reloc_code_real_type r)
3664 {
3665 if (r == BFD_RELOC_NONE)
3666 {
3667 if (size == 4)
3668 r = BFD_RELOC_32;
3669 if (size == 2)
3670 r = BFD_RELOC_16;
3671 if (size == 1)
3672 r = BFD_RELOC_8;
3673 }
3674
3675 if (exp != NULL)
3676 fix_new_exp (frag, where, size, exp, 0, r);
3677 else
3678 fix_new (frag, where, size, NULL, 0, 0, r);
3679 }
3680
3681 bfd_boolean
v850_fix_adjustable(fixS * fixP)3682 v850_fix_adjustable (fixS *fixP)
3683 {
3684 if (fixP->fx_addsy == NULL)
3685 return 1;
3686
3687 /* Don't adjust function names. */
3688 if (S_IS_FUNCTION (fixP->fx_addsy))
3689 return 0;
3690
3691 /* We need the symbol name for the VTABLE entries. */
3692 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3693 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3694 return 0;
3695
3696 return 1;
3697 }
3698
3699 int
v850_force_relocation(struct fix * fixP)3700 v850_force_relocation (struct fix *fixP)
3701 {
3702 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3703 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
3704 return 1;
3705
3706 if (v850_relax
3707 && (fixP->fx_pcrel
3708 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN
3709 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL
3710 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL
3711 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL
3712 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL
3713 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL
3714 || fixP->fx_r_type >= BFD_RELOC_UNUSED))
3715 return 1;
3716
3717 return generic_force_reloc (fixP);
3718 }
3719