1# Check 32bit AVX512{CD,VL} instructions 2 3 .allow_index_reg 4 .text 5_start: 6 vpconflictd %xmm5, %xmm6{%k7} # AVX512{CD,VL} 7 vpconflictd %xmm5, %xmm6{%k7}{z} # AVX512{CD,VL} 8 vpconflictd (%ecx), %xmm6{%k7} # AVX512{CD,VL} 9 vpconflictd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{CD,VL} 10 vpconflictd (%eax){1to4}, %xmm6{%k7} # AVX512{CD,VL} 11 vpconflictd 2032(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 12 vpconflictd 2048(%edx), %xmm6{%k7} # AVX512{CD,VL} 13 vpconflictd -2048(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 14 vpconflictd -2064(%edx), %xmm6{%k7} # AVX512{CD,VL} 15 vpconflictd 508(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} Disp8 16 vpconflictd 512(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} 17 vpconflictd -512(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} Disp8 18 vpconflictd -516(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} 19 vpconflictd %ymm5, %ymm6{%k7} # AVX512{CD,VL} 20 vpconflictd %ymm5, %ymm6{%k7}{z} # AVX512{CD,VL} 21 vpconflictd (%ecx), %ymm6{%k7} # AVX512{CD,VL} 22 vpconflictd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{CD,VL} 23 vpconflictd (%eax){1to8}, %ymm6{%k7} # AVX512{CD,VL} 24 vpconflictd 4064(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 25 vpconflictd 4096(%edx), %ymm6{%k7} # AVX512{CD,VL} 26 vpconflictd -4096(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 27 vpconflictd -4128(%edx), %ymm6{%k7} # AVX512{CD,VL} 28 vpconflictd 508(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} Disp8 29 vpconflictd 512(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} 30 vpconflictd -512(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} Disp8 31 vpconflictd -516(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} 32 vpconflictq %xmm5, %xmm6{%k7} # AVX512{CD,VL} 33 vpconflictq %xmm5, %xmm6{%k7}{z} # AVX512{CD,VL} 34 vpconflictq (%ecx), %xmm6{%k7} # AVX512{CD,VL} 35 vpconflictq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{CD,VL} 36 vpconflictq (%eax){1to2}, %xmm6{%k7} # AVX512{CD,VL} 37 vpconflictq 2032(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 38 vpconflictq 2048(%edx), %xmm6{%k7} # AVX512{CD,VL} 39 vpconflictq -2048(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 40 vpconflictq -2064(%edx), %xmm6{%k7} # AVX512{CD,VL} 41 vpconflictq 1016(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} Disp8 42 vpconflictq 1024(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} 43 vpconflictq -1024(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} Disp8 44 vpconflictq -1032(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} 45 vpconflictq %ymm5, %ymm6{%k7} # AVX512{CD,VL} 46 vpconflictq %ymm5, %ymm6{%k7}{z} # AVX512{CD,VL} 47 vpconflictq (%ecx), %ymm6{%k7} # AVX512{CD,VL} 48 vpconflictq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{CD,VL} 49 vpconflictq (%eax){1to4}, %ymm6{%k7} # AVX512{CD,VL} 50 vpconflictq 4064(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 51 vpconflictq 4096(%edx), %ymm6{%k7} # AVX512{CD,VL} 52 vpconflictq -4096(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 53 vpconflictq -4128(%edx), %ymm6{%k7} # AVX512{CD,VL} 54 vpconflictq 1016(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} Disp8 55 vpconflictq 1024(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} 56 vpconflictq -1024(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} Disp8 57 vpconflictq -1032(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} 58 vplzcntd %xmm5, %xmm6{%k7} # AVX512{CD,VL} 59 vplzcntd %xmm5, %xmm6{%k7}{z} # AVX512{CD,VL} 60 vplzcntd (%ecx), %xmm6{%k7} # AVX512{CD,VL} 61 vplzcntd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{CD,VL} 62 vplzcntd (%eax){1to4}, %xmm6{%k7} # AVX512{CD,VL} 63 vplzcntd 2032(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 64 vplzcntd 2048(%edx), %xmm6{%k7} # AVX512{CD,VL} 65 vplzcntd -2048(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 66 vplzcntd -2064(%edx), %xmm6{%k7} # AVX512{CD,VL} 67 vplzcntd 508(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} Disp8 68 vplzcntd 512(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} 69 vplzcntd -512(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} Disp8 70 vplzcntd -516(%edx){1to4}, %xmm6{%k7} # AVX512{CD,VL} 71 vplzcntd %ymm5, %ymm6{%k7} # AVX512{CD,VL} 72 vplzcntd %ymm5, %ymm6{%k7}{z} # AVX512{CD,VL} 73 vplzcntd (%ecx), %ymm6{%k7} # AVX512{CD,VL} 74 vplzcntd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{CD,VL} 75 vplzcntd (%eax){1to8}, %ymm6{%k7} # AVX512{CD,VL} 76 vplzcntd 4064(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 77 vplzcntd 4096(%edx), %ymm6{%k7} # AVX512{CD,VL} 78 vplzcntd -4096(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 79 vplzcntd -4128(%edx), %ymm6{%k7} # AVX512{CD,VL} 80 vplzcntd 508(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} Disp8 81 vplzcntd 512(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} 82 vplzcntd -512(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} Disp8 83 vplzcntd -516(%edx){1to8}, %ymm6{%k7} # AVX512{CD,VL} 84 vplzcntq %xmm5, %xmm6{%k7} # AVX512{CD,VL} 85 vplzcntq %xmm5, %xmm6{%k7}{z} # AVX512{CD,VL} 86 vplzcntq (%ecx), %xmm6{%k7} # AVX512{CD,VL} 87 vplzcntq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{CD,VL} 88 vplzcntq (%eax){1to2}, %xmm6{%k7} # AVX512{CD,VL} 89 vplzcntq 2032(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 90 vplzcntq 2048(%edx), %xmm6{%k7} # AVX512{CD,VL} 91 vplzcntq -2048(%edx), %xmm6{%k7} # AVX512{CD,VL} Disp8 92 vplzcntq -2064(%edx), %xmm6{%k7} # AVX512{CD,VL} 93 vplzcntq 1016(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} Disp8 94 vplzcntq 1024(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} 95 vplzcntq -1024(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} Disp8 96 vplzcntq -1032(%edx){1to2}, %xmm6{%k7} # AVX512{CD,VL} 97 vplzcntq %ymm5, %ymm6{%k7} # AVX512{CD,VL} 98 vplzcntq %ymm5, %ymm6{%k7}{z} # AVX512{CD,VL} 99 vplzcntq (%ecx), %ymm6{%k7} # AVX512{CD,VL} 100 vplzcntq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{CD,VL} 101 vplzcntq (%eax){1to4}, %ymm6{%k7} # AVX512{CD,VL} 102 vplzcntq 4064(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 103 vplzcntq 4096(%edx), %ymm6{%k7} # AVX512{CD,VL} 104 vplzcntq -4096(%edx), %ymm6{%k7} # AVX512{CD,VL} Disp8 105 vplzcntq -4128(%edx), %ymm6{%k7} # AVX512{CD,VL} 106 vplzcntq 1016(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} Disp8 107 vplzcntq 1024(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} 108 vplzcntq -1024(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} Disp8 109 vplzcntq -1032(%edx){1to4}, %ymm6{%k7} # AVX512{CD,VL} 110 vpbroadcastmw2d %k6, %xmm6 # AVX512{CD,VL} 111 vpbroadcastmw2d %k6, %ymm6 # AVX512{CD,VL} 112 vpbroadcastmb2q %k6, %xmm6 # AVX512{CD,VL} 113 vpbroadcastmb2q %k6, %ymm6 # AVX512{CD,VL} 114 115 .intel_syntax noprefix 116 vpconflictd xmm6{k7}, xmm5 # AVX512{CD,VL} 117 vpconflictd xmm6{k7}{z}, xmm5 # AVX512{CD,VL} 118 vpconflictd xmm6{k7}, XMMWORD PTR [ecx] # AVX512{CD,VL} 119 vpconflictd xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 120 vpconflictd xmm6{k7}, [eax]{1to4} # AVX512{CD,VL} 121 vpconflictd xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{CD,VL} Disp8 122 vpconflictd xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{CD,VL} 123 vpconflictd xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{CD,VL} Disp8 124 vpconflictd xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{CD,VL} 125 vpconflictd xmm6{k7}, [edx+508]{1to4} # AVX512{CD,VL} Disp8 126 vpconflictd xmm6{k7}, [edx+512]{1to4} # AVX512{CD,VL} 127 vpconflictd xmm6{k7}, [edx-512]{1to4} # AVX512{CD,VL} Disp8 128 vpconflictd xmm6{k7}, [edx-516]{1to4} # AVX512{CD,VL} 129 vpconflictd ymm6{k7}, ymm5 # AVX512{CD,VL} 130 vpconflictd ymm6{k7}{z}, ymm5 # AVX512{CD,VL} 131 vpconflictd ymm6{k7}, YMMWORD PTR [ecx] # AVX512{CD,VL} 132 vpconflictd ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 133 vpconflictd ymm6{k7}, [eax]{1to8} # AVX512{CD,VL} 134 vpconflictd ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{CD,VL} Disp8 135 vpconflictd ymm6{k7}, YMMWORD PTR [edx+4096] # AVX512{CD,VL} 136 vpconflictd ymm6{k7}, YMMWORD PTR [edx-4096] # AVX512{CD,VL} Disp8 137 vpconflictd ymm6{k7}, YMMWORD PTR [edx-4128] # AVX512{CD,VL} 138 vpconflictd ymm6{k7}, [edx+508]{1to8} # AVX512{CD,VL} Disp8 139 vpconflictd ymm6{k7}, [edx+512]{1to8} # AVX512{CD,VL} 140 vpconflictd ymm6{k7}, [edx-512]{1to8} # AVX512{CD,VL} Disp8 141 vpconflictd ymm6{k7}, [edx-516]{1to8} # AVX512{CD,VL} 142 vpconflictq xmm6{k7}, xmm5 # AVX512{CD,VL} 143 vpconflictq xmm6{k7}{z}, xmm5 # AVX512{CD,VL} 144 vpconflictq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{CD,VL} 145 vpconflictq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 146 vpconflictq xmm6{k7}, [eax]{1to2} # AVX512{CD,VL} 147 vpconflictq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{CD,VL} Disp8 148 vpconflictq xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{CD,VL} 149 vpconflictq xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{CD,VL} Disp8 150 vpconflictq xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{CD,VL} 151 vpconflictq xmm6{k7}, [edx+1016]{1to2} # AVX512{CD,VL} Disp8 152 vpconflictq xmm6{k7}, [edx+1024]{1to2} # AVX512{CD,VL} 153 vpconflictq xmm6{k7}, [edx-1024]{1to2} # AVX512{CD,VL} Disp8 154 vpconflictq xmm6{k7}, [edx-1032]{1to2} # AVX512{CD,VL} 155 vpconflictq ymm6{k7}, ymm5 # AVX512{CD,VL} 156 vpconflictq ymm6{k7}{z}, ymm5 # AVX512{CD,VL} 157 vpconflictq ymm6{k7}, YMMWORD PTR [ecx] # AVX512{CD,VL} 158 vpconflictq ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 159 vpconflictq ymm6{k7}, [eax]{1to4} # AVX512{CD,VL} 160 vpconflictq ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{CD,VL} Disp8 161 vpconflictq ymm6{k7}, YMMWORD PTR [edx+4096] # AVX512{CD,VL} 162 vpconflictq ymm6{k7}, YMMWORD PTR [edx-4096] # AVX512{CD,VL} Disp8 163 vpconflictq ymm6{k7}, YMMWORD PTR [edx-4128] # AVX512{CD,VL} 164 vpconflictq ymm6{k7}, [edx+1016]{1to4} # AVX512{CD,VL} Disp8 165 vpconflictq ymm6{k7}, [edx+1024]{1to4} # AVX512{CD,VL} 166 vpconflictq ymm6{k7}, [edx-1024]{1to4} # AVX512{CD,VL} Disp8 167 vpconflictq ymm6{k7}, [edx-1032]{1to4} # AVX512{CD,VL} 168 vplzcntd xmm6{k7}, xmm5 # AVX512{CD,VL} 169 vplzcntd xmm6{k7}{z}, xmm5 # AVX512{CD,VL} 170 vplzcntd xmm6{k7}, XMMWORD PTR [ecx] # AVX512{CD,VL} 171 vplzcntd xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 172 vplzcntd xmm6{k7}, [eax]{1to4} # AVX512{CD,VL} 173 vplzcntd xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{CD,VL} Disp8 174 vplzcntd xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{CD,VL} 175 vplzcntd xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{CD,VL} Disp8 176 vplzcntd xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{CD,VL} 177 vplzcntd xmm6{k7}, [edx+508]{1to4} # AVX512{CD,VL} Disp8 178 vplzcntd xmm6{k7}, [edx+512]{1to4} # AVX512{CD,VL} 179 vplzcntd xmm6{k7}, [edx-512]{1to4} # AVX512{CD,VL} Disp8 180 vplzcntd xmm6{k7}, [edx-516]{1to4} # AVX512{CD,VL} 181 vplzcntd ymm6{k7}, ymm5 # AVX512{CD,VL} 182 vplzcntd ymm6{k7}{z}, ymm5 # AVX512{CD,VL} 183 vplzcntd ymm6{k7}, YMMWORD PTR [ecx] # AVX512{CD,VL} 184 vplzcntd ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 185 vplzcntd ymm6{k7}, [eax]{1to8} # AVX512{CD,VL} 186 vplzcntd ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{CD,VL} Disp8 187 vplzcntd ymm6{k7}, YMMWORD PTR [edx+4096] # AVX512{CD,VL} 188 vplzcntd ymm6{k7}, YMMWORD PTR [edx-4096] # AVX512{CD,VL} Disp8 189 vplzcntd ymm6{k7}, YMMWORD PTR [edx-4128] # AVX512{CD,VL} 190 vplzcntd ymm6{k7}, [edx+508]{1to8} # AVX512{CD,VL} Disp8 191 vplzcntd ymm6{k7}, [edx+512]{1to8} # AVX512{CD,VL} 192 vplzcntd ymm6{k7}, [edx-512]{1to8} # AVX512{CD,VL} Disp8 193 vplzcntd ymm6{k7}, [edx-516]{1to8} # AVX512{CD,VL} 194 vplzcntq xmm6{k7}, xmm5 # AVX512{CD,VL} 195 vplzcntq xmm6{k7}{z}, xmm5 # AVX512{CD,VL} 196 vplzcntq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{CD,VL} 197 vplzcntq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 198 vplzcntq xmm6{k7}, [eax]{1to2} # AVX512{CD,VL} 199 vplzcntq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{CD,VL} Disp8 200 vplzcntq xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{CD,VL} 201 vplzcntq xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{CD,VL} Disp8 202 vplzcntq xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{CD,VL} 203 vplzcntq xmm6{k7}, [edx+1016]{1to2} # AVX512{CD,VL} Disp8 204 vplzcntq xmm6{k7}, [edx+1024]{1to2} # AVX512{CD,VL} 205 vplzcntq xmm6{k7}, [edx-1024]{1to2} # AVX512{CD,VL} Disp8 206 vplzcntq xmm6{k7}, [edx-1032]{1to2} # AVX512{CD,VL} 207 vplzcntq ymm6{k7}, ymm5 # AVX512{CD,VL} 208 vplzcntq ymm6{k7}{z}, ymm5 # AVX512{CD,VL} 209 vplzcntq ymm6{k7}, YMMWORD PTR [ecx] # AVX512{CD,VL} 210 vplzcntq ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{CD,VL} 211 vplzcntq ymm6{k7}, [eax]{1to4} # AVX512{CD,VL} 212 vplzcntq ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{CD,VL} Disp8 213 vplzcntq ymm6{k7}, YMMWORD PTR [edx+4096] # AVX512{CD,VL} 214 vplzcntq ymm6{k7}, YMMWORD PTR [edx-4096] # AVX512{CD,VL} Disp8 215 vplzcntq ymm6{k7}, YMMWORD PTR [edx-4128] # AVX512{CD,VL} 216 vplzcntq ymm6{k7}, [edx+1016]{1to4} # AVX512{CD,VL} Disp8 217 vplzcntq ymm6{k7}, [edx+1024]{1to4} # AVX512{CD,VL} 218 vplzcntq ymm6{k7}, [edx-1024]{1to4} # AVX512{CD,VL} Disp8 219 vplzcntq ymm6{k7}, [edx-1032]{1to4} # AVX512{CD,VL} 220 vpbroadcastmw2d xmm6, k6 # AVX512{CD,VL} 221 vpbroadcastmw2d ymm6, k6 # AVX512{CD,VL} 222 vpbroadcastmb2q xmm6, k6 # AVX512{CD,VL} 223 vpbroadcastmb2q ymm6, k6 # AVX512{CD,VL} 224