xref: /hardware/intel/img/psb_video/src/hwdefs/msvdx_vec_vp8_line_store_mem_io2.h

/*
 * Copyright (c) 2011 Intel Corporation. All Rights Reserved.
 * Copyright (c) Imagination Technologies Limited, UK
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */


/*****************************************************************************

 @File         msvdx_vec_vp8_line_store_mem_io2.h

 @Title        MSVDX Offsets

 @Platform     </b>\n

 @Description  </b>\n This file contains the MSVDX_VEC_VP8_LINE_STORE_MEM_IO2_H Defintions.

******************************************************************************/

#if !defined (__MSVDX_VEC_VP8_LINE_STORE_MEM_IO2_H__)
#define __MSVDX_VEC_VP8_LINE_STORE_MEM_IO2_H__

#ifdef __cplusplus
extern "C" {
#endif


#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_OFFSET	(0x0800)

// MSVDX_VEC_LINE_STORE_RAM, MB_START_PROBS_REG_00, SEGMENT_ID_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_00_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MB_START_PROBS_REG_00, SEGMENT_ID_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_01_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MB_START_PROBS_REG_00, SEGMENT_ID_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_02_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MB_START_PROBS_REG_00, SKIP_FALSE_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SKIP_FALSE_PROBS_00_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SKIP_FALSE_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SKIP_FALSE_PROBS_00_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SKIP_FALSE_PROBS_00_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_OFFSET	(0x0804)

// MSVDX_VEC_LINE_STORE_RAM, Y_MODE_PROBS_REG_00, Y_MODE_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, Y_MODE_PROBS_REG_00, Y_MODE_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, Y_MODE_PROBS_REG_00, Y_MODE_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, Y_MODE_PROBS_REG_00, Y_MODE_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_03_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_OFFSET	(0x0808)

// MSVDX_VEC_LINE_STORE_RAM, UV_MODE_PROBS_REG_00, UV_MODE_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, UV_MODE_PROBS_REG_00, UV_MODE_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, UV_MODE_PROBS_REG_00, UV_MODE_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_02_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_OFFSET	(0x080C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_00, KF_B_MODE_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_00_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_00, KF_B_MODE_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_01_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_00, KF_B_MODE_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_02_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_00, KF_B_MODE_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_03_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_03_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_00_KF_B_MODE_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_OFFSET	(0x0810)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_01, KF_B_MODE_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_04_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_04_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_01, KF_B_MODE_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_05_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_05_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_01, KF_B_MODE_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_06_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_06_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_01, KF_B_MODE_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_07_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_07_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_01_KF_B_MODE_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_OFFSET	(0x0814)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_02, KF_B_MODE_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_08_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_08_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_02, KF_B_MODE_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_09_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_09_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_02, KF_B_MODE_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_10_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_10_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_10_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_02, KF_B_MODE_PROBS_11
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_11_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_11_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_11_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_02_KF_B_MODE_PROBS_11_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_OFFSET	(0x0818)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_03, KF_B_MODE_PROBS_12
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_12_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_12_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_12_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_12_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_03, KF_B_MODE_PROBS_13
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_13_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_13_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_13_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_13_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_03, KF_B_MODE_PROBS_14
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_14_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_14_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_14_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_14_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_03, KF_B_MODE_PROBS_15
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_15_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_15_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_15_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_03_KF_B_MODE_PROBS_15_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_OFFSET	(0x081C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_04, KF_B_MODE_PROBS_16
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_16_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_16_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_16_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_16_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_04, KF_B_MODE_PROBS_17
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_17_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_17_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_17_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_17_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_04, KF_B_MODE_PROBS_18
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_18_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_18_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_18_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_18_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_04, KF_B_MODE_PROBS_19
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_19_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_19_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_19_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_04_KF_B_MODE_PROBS_19_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_OFFSET	(0x0820)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_05, KF_B_MODE_PROBS_20
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_20_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_20_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_20_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_20_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_05, KF_B_MODE_PROBS_21
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_21_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_21_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_21_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_21_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_05, KF_B_MODE_PROBS_22
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_22_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_22_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_22_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_22_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_05, KF_B_MODE_PROBS_23
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_23_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_23_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_23_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_05_KF_B_MODE_PROBS_23_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_OFFSET	(0x0824)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_06, KF_B_MODE_PROBS_24
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_24_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_24_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_24_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_24_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_06, KF_B_MODE_PROBS_25
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_25_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_25_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_25_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_25_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_06, KF_B_MODE_PROBS_26
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_26_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_26_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_26_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_26_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_06, KF_B_MODE_PROBS_27
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_27_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_27_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_27_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_06_KF_B_MODE_PROBS_27_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_OFFSET	(0x0828)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_07, KF_B_MODE_PROBS_28
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_28_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_28_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_28_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_28_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_07, KF_B_MODE_PROBS_29
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_29_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_29_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_29_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_29_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_07, KF_B_MODE_PROBS_30
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_30_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_30_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_30_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_30_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_07, KF_B_MODE_PROBS_31
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_31_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_31_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_31_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_07_KF_B_MODE_PROBS_31_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_OFFSET	(0x082C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_08, KF_B_MODE_PROBS_32
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_32_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_32_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_32_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_32_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_08, KF_B_MODE_PROBS_33
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_33_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_33_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_33_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_33_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_08, KF_B_MODE_PROBS_34
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_34_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_34_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_34_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_34_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_08, KF_B_MODE_PROBS_35
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_35_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_35_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_35_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_08_KF_B_MODE_PROBS_35_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_OFFSET	(0x0830)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_09, KF_B_MODE_PROBS_36
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_36_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_36_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_36_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_36_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_09, KF_B_MODE_PROBS_37
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_37_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_37_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_37_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_37_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_09, KF_B_MODE_PROBS_38
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_38_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_38_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_38_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_38_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_09, KF_B_MODE_PROBS_39
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_39_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_39_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_39_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_09_KF_B_MODE_PROBS_39_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_OFFSET	(0x0834)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_10, KF_B_MODE_PROBS_40
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_40_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_40_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_40_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_40_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_10, KF_B_MODE_PROBS_41
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_41_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_41_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_41_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_41_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_10, KF_B_MODE_PROBS_42
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_42_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_42_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_42_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_42_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_10, KF_B_MODE_PROBS_43
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_43_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_43_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_43_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_10_KF_B_MODE_PROBS_43_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_OFFSET	(0x0838)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_11, KF_B_MODE_PROBS_44
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_44_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_44_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_44_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_44_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_11, KF_B_MODE_PROBS_45
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_45_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_45_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_45_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_45_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_11, KF_B_MODE_PROBS_46
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_46_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_46_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_46_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_46_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_11, KF_B_MODE_PROBS_47
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_47_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_47_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_47_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_11_KF_B_MODE_PROBS_47_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_OFFSET	(0x083C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_12, KF_B_MODE_PROBS_48
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_48_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_48_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_48_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_48_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_12, KF_B_MODE_PROBS_49
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_49_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_49_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_49_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_49_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_12, KF_B_MODE_PROBS_50
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_50_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_50_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_50_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_50_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_12, KF_B_MODE_PROBS_51
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_51_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_51_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_51_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_12_KF_B_MODE_PROBS_51_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_OFFSET	(0x0840)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_13, KF_B_MODE_PROBS_52
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_52_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_52_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_52_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_52_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_13, KF_B_MODE_PROBS_53
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_53_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_53_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_53_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_53_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_13, KF_B_MODE_PROBS_54
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_54_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_54_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_54_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_54_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_13, KF_B_MODE_PROBS_55
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_55_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_55_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_55_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_13_KF_B_MODE_PROBS_55_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_OFFSET	(0x0844)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_14, KF_B_MODE_PROBS_56
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_56_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_56_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_56_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_56_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_14, KF_B_MODE_PROBS_57
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_57_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_57_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_57_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_57_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_14, KF_B_MODE_PROBS_58
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_58_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_58_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_58_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_58_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_14, KF_B_MODE_PROBS_59
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_59_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_59_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_59_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_14_KF_B_MODE_PROBS_59_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_OFFSET	(0x0848)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_15, KF_B_MODE_PROBS_60
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_60_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_60_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_60_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_60_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_15, KF_B_MODE_PROBS_61
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_61_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_61_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_61_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_61_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_15, KF_B_MODE_PROBS_62
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_62_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_62_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_62_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_62_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_15, KF_B_MODE_PROBS_63
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_63_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_63_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_63_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_15_KF_B_MODE_PROBS_63_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_OFFSET	(0x084C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_16, KF_B_MODE_PROBS_64
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_64_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_64_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_64_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_64_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_16, KF_B_MODE_PROBS_65
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_65_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_65_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_65_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_65_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_16, KF_B_MODE_PROBS_66
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_66_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_66_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_66_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_66_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_16, KF_B_MODE_PROBS_67
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_67_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_67_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_67_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_16_KF_B_MODE_PROBS_67_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_OFFSET	(0x0850)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_17, KF_B_MODE_PROBS_68
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_68_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_68_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_68_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_68_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_17, KF_B_MODE_PROBS_69
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_69_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_69_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_69_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_69_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_17, KF_B_MODE_PROBS_70
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_70_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_70_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_70_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_70_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_17, KF_B_MODE_PROBS_71
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_71_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_71_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_71_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_17_KF_B_MODE_PROBS_71_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_OFFSET	(0x0854)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_18, KF_B_MODE_PROBS_72
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_72_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_72_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_72_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_72_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_18, KF_B_MODE_PROBS_73
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_73_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_73_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_73_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_73_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_18, KF_B_MODE_PROBS_74
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_74_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_74_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_74_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_74_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_18, KF_B_MODE_PROBS_75
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_75_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_75_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_75_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_18_KF_B_MODE_PROBS_75_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_OFFSET	(0x0858)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_19, KF_B_MODE_PROBS_76
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_76_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_76_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_76_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_76_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_19, KF_B_MODE_PROBS_77
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_77_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_77_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_77_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_77_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_19, KF_B_MODE_PROBS_78
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_78_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_78_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_78_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_78_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_19, KF_B_MODE_PROBS_79
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_79_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_79_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_79_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_19_KF_B_MODE_PROBS_79_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_OFFSET	(0x085C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_20, KF_B_MODE_PROBS_80
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_80_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_80_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_80_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_80_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_20, KF_B_MODE_PROBS_81
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_81_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_81_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_81_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_81_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_20, KF_B_MODE_PROBS_82
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_82_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_82_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_82_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_82_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_20, KF_B_MODE_PROBS_83
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_83_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_83_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_83_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_20_KF_B_MODE_PROBS_83_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_OFFSET	(0x0860)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_21, KF_B_MODE_PROBS_84
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_84_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_84_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_84_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_84_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_21, KF_B_MODE_PROBS_85
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_85_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_85_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_85_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_85_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_21, KF_B_MODE_PROBS_86
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_86_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_86_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_86_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_86_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_21, KF_B_MODE_PROBS_87
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_87_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_87_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_87_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_21_KF_B_MODE_PROBS_87_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_OFFSET	(0x0864)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_22, KF_B_MODE_PROBS_88
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_88_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_88_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_88_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_88_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_22, KF_B_MODE_PROBS_89
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_89_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_89_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_89_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_89_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_22, KF_B_MODE_PROBS_90
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_90_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_90_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_90_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_90_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_22, KF_B_MODE_PROBS_91
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_91_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_91_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_91_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_22_KF_B_MODE_PROBS_91_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_OFFSET	(0x0868)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_23, KF_B_MODE_PROBS_92
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_92_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_92_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_92_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_92_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_23, KF_B_MODE_PROBS_93
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_93_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_93_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_93_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_93_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_23, KF_B_MODE_PROBS_94
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_94_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_94_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_94_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_94_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_23, KF_B_MODE_PROBS_95
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_95_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_95_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_95_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_23_KF_B_MODE_PROBS_95_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_OFFSET	(0x086C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_24, KF_B_MODE_PROBS_96
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_96_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_96_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_96_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_96_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_24, KF_B_MODE_PROBS_97
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_97_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_97_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_97_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_97_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_24, KF_B_MODE_PROBS_98
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_98_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_98_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_98_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_98_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_24, KF_B_MODE_PROBS_99
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_99_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_99_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_99_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_24_KF_B_MODE_PROBS_99_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_OFFSET	(0x0870)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_25, KF_B_MODE_PROBS_100
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_100_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_100_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_100_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_100_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_25, KF_B_MODE_PROBS_101
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_101_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_101_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_101_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_101_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_25, KF_B_MODE_PROBS_102
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_102_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_102_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_102_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_102_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_25, KF_B_MODE_PROBS_103
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_103_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_103_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_103_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_25_KF_B_MODE_PROBS_103_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_OFFSET	(0x0874)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_26, KF_B_MODE_PROBS_104
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_104_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_104_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_104_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_104_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_26, KF_B_MODE_PROBS_105
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_105_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_105_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_105_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_105_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_26, KF_B_MODE_PROBS_106
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_106_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_106_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_106_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_106_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_26, KF_B_MODE_PROBS_107
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_107_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_107_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_107_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_26_KF_B_MODE_PROBS_107_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_OFFSET	(0x0878)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_27, KF_B_MODE_PROBS_108
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_108_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_108_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_108_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_108_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_27, KF_B_MODE_PROBS_109
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_109_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_109_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_109_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_109_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_27, KF_B_MODE_PROBS_110
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_110_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_110_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_110_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_110_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_27, KF_B_MODE_PROBS_111
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_111_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_111_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_111_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_27_KF_B_MODE_PROBS_111_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_OFFSET	(0x087C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_28, KF_B_MODE_PROBS_112
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_112_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_112_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_112_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_112_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_28, KF_B_MODE_PROBS_113
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_113_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_113_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_113_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_113_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_28, KF_B_MODE_PROBS_114
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_114_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_114_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_114_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_114_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_28, KF_B_MODE_PROBS_115
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_115_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_115_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_115_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_28_KF_B_MODE_PROBS_115_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_OFFSET	(0x0880)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_29, KF_B_MODE_PROBS_116
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_116_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_116_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_116_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_116_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_29, KF_B_MODE_PROBS_117
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_117_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_117_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_117_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_117_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_29, KF_B_MODE_PROBS_118
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_118_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_118_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_118_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_118_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_29, KF_B_MODE_PROBS_119
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_119_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_119_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_119_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_29_KF_B_MODE_PROBS_119_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_OFFSET	(0x0884)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_30, KF_B_MODE_PROBS_120
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_120_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_120_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_120_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_120_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_30, KF_B_MODE_PROBS_121
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_121_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_121_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_121_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_121_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_30, KF_B_MODE_PROBS_122
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_122_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_122_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_122_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_122_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_30, KF_B_MODE_PROBS_123
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_123_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_123_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_123_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_30_KF_B_MODE_PROBS_123_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_OFFSET	(0x0888)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_31, KF_B_MODE_PROBS_124
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_124_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_124_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_124_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_124_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_31, KF_B_MODE_PROBS_125
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_125_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_125_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_125_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_125_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_31, KF_B_MODE_PROBS_126
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_126_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_126_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_126_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_126_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_31, KF_B_MODE_PROBS_127
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_127_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_127_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_127_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_31_KF_B_MODE_PROBS_127_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_OFFSET	(0x088C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_32, KF_B_MODE_PROBS_128
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_128_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_128_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_128_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_128_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_32, KF_B_MODE_PROBS_129
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_129_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_129_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_129_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_129_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_32, KF_B_MODE_PROBS_130
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_130_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_130_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_130_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_130_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_32, KF_B_MODE_PROBS_131
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_131_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_131_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_131_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_32_KF_B_MODE_PROBS_131_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_OFFSET	(0x0890)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_33, KF_B_MODE_PROBS_132
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_132_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_132_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_132_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_132_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_33, KF_B_MODE_PROBS_133
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_133_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_133_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_133_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_133_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_33, KF_B_MODE_PROBS_134
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_134_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_134_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_134_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_134_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_33, KF_B_MODE_PROBS_135
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_135_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_135_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_135_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_33_KF_B_MODE_PROBS_135_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_OFFSET	(0x0894)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_34, KF_B_MODE_PROBS_136
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_136_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_136_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_136_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_136_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_34, KF_B_MODE_PROBS_137
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_137_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_137_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_137_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_137_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_34, KF_B_MODE_PROBS_138
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_138_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_138_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_138_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_138_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_34, KF_B_MODE_PROBS_139
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_139_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_139_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_139_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_34_KF_B_MODE_PROBS_139_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_OFFSET	(0x0898)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_35, KF_B_MODE_PROBS_140
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_140_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_140_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_140_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_140_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_35, KF_B_MODE_PROBS_141
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_141_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_141_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_141_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_141_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_35, KF_B_MODE_PROBS_142
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_142_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_142_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_142_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_142_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_35, KF_B_MODE_PROBS_143
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_143_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_143_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_143_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_35_KF_B_MODE_PROBS_143_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_OFFSET	(0x089C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_36, KF_B_MODE_PROBS_144
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_144_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_144_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_144_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_144_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_36, KF_B_MODE_PROBS_145
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_145_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_145_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_145_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_145_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_36, KF_B_MODE_PROBS_146
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_146_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_146_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_146_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_146_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_36, KF_B_MODE_PROBS_147
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_147_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_147_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_147_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_36_KF_B_MODE_PROBS_147_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_OFFSET	(0x08A0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_37, KF_B_MODE_PROBS_148
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_148_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_148_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_148_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_148_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_37, KF_B_MODE_PROBS_149
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_149_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_149_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_149_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_149_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_37, KF_B_MODE_PROBS_150
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_150_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_150_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_150_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_150_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_37, KF_B_MODE_PROBS_151
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_151_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_151_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_151_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_37_KF_B_MODE_PROBS_151_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_OFFSET	(0x08A4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_38, KF_B_MODE_PROBS_152
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_152_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_152_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_152_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_152_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_38, KF_B_MODE_PROBS_153
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_153_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_153_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_153_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_153_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_38, KF_B_MODE_PROBS_154
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_154_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_154_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_154_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_154_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_38, KF_B_MODE_PROBS_155
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_155_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_155_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_155_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_38_KF_B_MODE_PROBS_155_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_OFFSET	(0x08A8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_39, KF_B_MODE_PROBS_156
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_156_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_156_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_156_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_156_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_39, KF_B_MODE_PROBS_157
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_157_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_157_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_157_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_157_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_39, KF_B_MODE_PROBS_158
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_158_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_158_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_158_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_158_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_39, KF_B_MODE_PROBS_159
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_159_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_159_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_159_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_39_KF_B_MODE_PROBS_159_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_OFFSET	(0x08AC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_40, KF_B_MODE_PROBS_160
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_160_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_160_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_160_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_160_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_40, KF_B_MODE_PROBS_161
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_161_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_161_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_161_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_161_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_40, KF_B_MODE_PROBS_162
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_162_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_162_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_162_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_162_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_40, KF_B_MODE_PROBS_163
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_163_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_163_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_163_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_40_KF_B_MODE_PROBS_163_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_OFFSET	(0x08B0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_41, KF_B_MODE_PROBS_164
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_164_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_164_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_164_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_164_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_41, KF_B_MODE_PROBS_165
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_165_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_165_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_165_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_165_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_41, KF_B_MODE_PROBS_166
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_166_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_166_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_166_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_166_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_41, KF_B_MODE_PROBS_167
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_167_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_167_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_167_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_41_KF_B_MODE_PROBS_167_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_OFFSET	(0x08B4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_42, KF_B_MODE_PROBS_168
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_168_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_168_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_168_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_168_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_42, KF_B_MODE_PROBS_169
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_169_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_169_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_169_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_169_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_42, KF_B_MODE_PROBS_170
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_170_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_170_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_170_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_170_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_42, KF_B_MODE_PROBS_171
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_171_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_171_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_171_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_42_KF_B_MODE_PROBS_171_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_OFFSET	(0x08B8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_43, KF_B_MODE_PROBS_172
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_172_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_172_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_172_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_172_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_43, KF_B_MODE_PROBS_173
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_173_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_173_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_173_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_173_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_43, KF_B_MODE_PROBS_174
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_174_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_174_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_174_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_174_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_43, KF_B_MODE_PROBS_175
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_175_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_175_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_175_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_43_KF_B_MODE_PROBS_175_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_OFFSET	(0x08BC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_44, KF_B_MODE_PROBS_176
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_176_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_176_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_176_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_176_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_44, KF_B_MODE_PROBS_177
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_177_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_177_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_177_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_177_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_44, KF_B_MODE_PROBS_178
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_178_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_178_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_178_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_178_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_44, KF_B_MODE_PROBS_179
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_179_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_179_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_179_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_44_KF_B_MODE_PROBS_179_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_OFFSET	(0x08C0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_45, KF_B_MODE_PROBS_180
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_180_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_180_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_180_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_180_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_45, KF_B_MODE_PROBS_181
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_181_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_181_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_181_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_181_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_45, KF_B_MODE_PROBS_182
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_182_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_182_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_182_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_182_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_45, KF_B_MODE_PROBS_183
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_183_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_183_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_183_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_45_KF_B_MODE_PROBS_183_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_OFFSET	(0x08C4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_46, KF_B_MODE_PROBS_184
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_184_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_184_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_184_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_184_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_46, KF_B_MODE_PROBS_185
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_185_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_185_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_185_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_185_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_46, KF_B_MODE_PROBS_186
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_186_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_186_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_186_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_186_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_46, KF_B_MODE_PROBS_187
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_187_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_187_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_187_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_46_KF_B_MODE_PROBS_187_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_OFFSET	(0x08C8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_47, KF_B_MODE_PROBS_188
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_188_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_188_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_188_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_188_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_47, KF_B_MODE_PROBS_189
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_189_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_189_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_189_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_189_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_47, KF_B_MODE_PROBS_190
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_190_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_190_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_190_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_190_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_47, KF_B_MODE_PROBS_191
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_191_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_191_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_191_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_47_KF_B_MODE_PROBS_191_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_OFFSET	(0x08CC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_48, KF_B_MODE_PROBS_192
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_192_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_192_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_192_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_192_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_48, KF_B_MODE_PROBS_193
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_193_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_193_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_193_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_193_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_48, KF_B_MODE_PROBS_194
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_194_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_194_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_194_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_194_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_48, KF_B_MODE_PROBS_195
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_195_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_195_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_195_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_48_KF_B_MODE_PROBS_195_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_OFFSET	(0x08D0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_49, KF_B_MODE_PROBS_196
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_196_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_196_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_196_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_196_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_49, KF_B_MODE_PROBS_197
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_197_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_197_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_197_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_197_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_49, KF_B_MODE_PROBS_198
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_198_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_198_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_198_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_198_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_49, KF_B_MODE_PROBS_199
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_199_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_199_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_199_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_49_KF_B_MODE_PROBS_199_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_OFFSET	(0x08D4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_50, KF_B_MODE_PROBS_200
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_200_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_200_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_200_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_200_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_50, KF_B_MODE_PROBS_201
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_201_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_201_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_201_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_201_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_50, KF_B_MODE_PROBS_202
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_202_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_202_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_202_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_202_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_50, KF_B_MODE_PROBS_203
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_203_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_203_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_203_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_50_KF_B_MODE_PROBS_203_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_OFFSET	(0x08D8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_51, KF_B_MODE_PROBS_204
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_204_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_204_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_204_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_204_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_51, KF_B_MODE_PROBS_205
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_205_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_205_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_205_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_205_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_51, KF_B_MODE_PROBS_206
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_206_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_206_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_206_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_206_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_51, KF_B_MODE_PROBS_207
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_207_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_207_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_207_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_51_KF_B_MODE_PROBS_207_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_OFFSET	(0x08DC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_52, KF_B_MODE_PROBS_208
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_208_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_208_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_208_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_208_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_52, KF_B_MODE_PROBS_209
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_209_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_209_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_209_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_209_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_52, KF_B_MODE_PROBS_210
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_210_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_210_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_210_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_210_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_52, KF_B_MODE_PROBS_211
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_211_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_211_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_211_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_52_KF_B_MODE_PROBS_211_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_OFFSET	(0x08E0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_53, KF_B_MODE_PROBS_212
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_212_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_212_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_212_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_212_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_53, KF_B_MODE_PROBS_213
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_213_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_213_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_213_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_213_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_53, KF_B_MODE_PROBS_214
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_214_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_214_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_214_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_214_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_53, KF_B_MODE_PROBS_215
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_215_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_215_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_215_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_53_KF_B_MODE_PROBS_215_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_OFFSET	(0x08E4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_54, KF_B_MODE_PROBS_216
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_216_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_216_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_216_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_216_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_54, KF_B_MODE_PROBS_217
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_217_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_217_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_217_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_217_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_54, KF_B_MODE_PROBS_218
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_218_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_218_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_218_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_218_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_54, KF_B_MODE_PROBS_219
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_219_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_219_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_219_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_54_KF_B_MODE_PROBS_219_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_OFFSET	(0x08E8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_55, KF_B_MODE_PROBS_220
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_220_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_220_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_220_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_220_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_55, KF_B_MODE_PROBS_221
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_221_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_221_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_221_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_221_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_55, KF_B_MODE_PROBS_222
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_222_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_222_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_222_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_222_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_55, KF_B_MODE_PROBS_223
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_223_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_223_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_223_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_55_KF_B_MODE_PROBS_223_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_OFFSET	(0x08EC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_56, KF_B_MODE_PROBS_224
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_224_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_224_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_224_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_224_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_56, KF_B_MODE_PROBS_225
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_225_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_225_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_225_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_225_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_56, KF_B_MODE_PROBS_226
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_226_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_226_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_226_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_226_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_56, KF_B_MODE_PROBS_227
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_227_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_227_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_227_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_56_KF_B_MODE_PROBS_227_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_OFFSET	(0x08F0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_57, KF_B_MODE_PROBS_228
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_228_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_228_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_228_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_228_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_57, KF_B_MODE_PROBS_229
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_229_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_229_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_229_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_229_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_57, KF_B_MODE_PROBS_230
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_230_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_230_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_230_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_230_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_57, KF_B_MODE_PROBS_231
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_231_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_231_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_231_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_57_KF_B_MODE_PROBS_231_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_OFFSET	(0x08F4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_58, KF_B_MODE_PROBS_232
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_232_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_232_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_232_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_232_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_58, KF_B_MODE_PROBS_233
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_233_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_233_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_233_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_233_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_58, KF_B_MODE_PROBS_234
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_234_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_234_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_234_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_234_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_58, KF_B_MODE_PROBS_235
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_235_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_235_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_235_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_58_KF_B_MODE_PROBS_235_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_OFFSET	(0x08F8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_59, KF_B_MODE_PROBS_236
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_236_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_236_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_236_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_236_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_59, KF_B_MODE_PROBS_237
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_237_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_237_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_237_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_237_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_59, KF_B_MODE_PROBS_238
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_238_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_238_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_238_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_238_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_59, KF_B_MODE_PROBS_239
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_239_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_239_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_239_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_59_KF_B_MODE_PROBS_239_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_OFFSET	(0x08FC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_60, KF_B_MODE_PROBS_240
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_240_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_240_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_240_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_240_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_60, KF_B_MODE_PROBS_241
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_241_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_241_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_241_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_241_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_60, KF_B_MODE_PROBS_242
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_242_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_242_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_242_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_242_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_60, KF_B_MODE_PROBS_243
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_243_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_243_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_243_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_60_KF_B_MODE_PROBS_243_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_OFFSET	(0x0900)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_61, KF_B_MODE_PROBS_244
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_244_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_244_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_244_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_244_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_61, KF_B_MODE_PROBS_245
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_245_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_245_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_245_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_245_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_61, KF_B_MODE_PROBS_246
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_246_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_246_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_246_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_246_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_61, KF_B_MODE_PROBS_247
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_247_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_247_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_247_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_61_KF_B_MODE_PROBS_247_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_OFFSET	(0x0904)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_62, KF_B_MODE_PROBS_248
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_248_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_248_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_248_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_248_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_62, KF_B_MODE_PROBS_249
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_249_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_249_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_249_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_249_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_62, KF_B_MODE_PROBS_250
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_250_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_250_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_250_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_250_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_62, KF_B_MODE_PROBS_251
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_251_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_251_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_251_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_62_KF_B_MODE_PROBS_251_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_OFFSET	(0x0908)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_63, KF_B_MODE_PROBS_252
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_252_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_252_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_252_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_252_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_63, KF_B_MODE_PROBS_253
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_253_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_253_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_253_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_253_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_63, KF_B_MODE_PROBS_254
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_254_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_254_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_254_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_254_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_63, KF_B_MODE_PROBS_255
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_255_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_255_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_255_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_63_KF_B_MODE_PROBS_255_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_OFFSET	(0x090C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_64, KF_B_MODE_PROBS_256
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_256_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_256_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_256_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_256_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_64, KF_B_MODE_PROBS_257
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_257_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_257_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_257_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_257_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_64, KF_B_MODE_PROBS_258
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_258_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_258_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_258_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_258_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_64, KF_B_MODE_PROBS_259
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_259_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_259_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_259_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_64_KF_B_MODE_PROBS_259_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_OFFSET	(0x0910)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_65, KF_B_MODE_PROBS_260
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_260_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_260_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_260_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_260_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_65, KF_B_MODE_PROBS_261
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_261_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_261_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_261_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_261_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_65, KF_B_MODE_PROBS_262
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_262_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_262_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_262_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_262_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_65, KF_B_MODE_PROBS_263
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_263_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_263_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_263_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_65_KF_B_MODE_PROBS_263_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_OFFSET	(0x0914)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_66, KF_B_MODE_PROBS_264
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_264_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_264_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_264_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_264_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_66, KF_B_MODE_PROBS_265
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_265_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_265_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_265_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_265_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_66, KF_B_MODE_PROBS_266
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_266_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_266_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_266_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_266_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_66, KF_B_MODE_PROBS_267
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_267_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_267_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_267_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_66_KF_B_MODE_PROBS_267_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_OFFSET	(0x0918)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_67, KF_B_MODE_PROBS_268
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_268_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_268_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_268_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_268_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_67, KF_B_MODE_PROBS_269
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_269_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_269_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_269_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_269_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_67, KF_B_MODE_PROBS_270
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_270_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_270_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_270_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_270_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_67, KF_B_MODE_PROBS_271
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_271_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_271_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_271_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_67_KF_B_MODE_PROBS_271_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_OFFSET	(0x091C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_68, KF_B_MODE_PROBS_272
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_272_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_272_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_272_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_272_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_68, KF_B_MODE_PROBS_273
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_273_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_273_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_273_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_273_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_68, KF_B_MODE_PROBS_274
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_274_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_274_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_274_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_274_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_68, KF_B_MODE_PROBS_275
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_275_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_275_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_275_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_68_KF_B_MODE_PROBS_275_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_OFFSET	(0x0920)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_69, KF_B_MODE_PROBS_276
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_276_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_276_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_276_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_276_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_69, KF_B_MODE_PROBS_277
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_277_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_277_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_277_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_277_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_69, KF_B_MODE_PROBS_278
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_278_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_278_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_278_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_278_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_69, KF_B_MODE_PROBS_279
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_279_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_279_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_279_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_69_KF_B_MODE_PROBS_279_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_OFFSET	(0x0924)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_70, KF_B_MODE_PROBS_280
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_280_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_280_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_280_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_280_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_70, KF_B_MODE_PROBS_281
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_281_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_281_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_281_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_281_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_70, KF_B_MODE_PROBS_282
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_282_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_282_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_282_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_282_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_70, KF_B_MODE_PROBS_283
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_283_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_283_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_283_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_70_KF_B_MODE_PROBS_283_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_OFFSET	(0x0928)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_71, KF_B_MODE_PROBS_284
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_284_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_284_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_284_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_284_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_71, KF_B_MODE_PROBS_285
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_285_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_285_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_285_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_285_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_71, KF_B_MODE_PROBS_286
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_286_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_286_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_286_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_286_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_71, KF_B_MODE_PROBS_287
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_287_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_287_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_287_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_71_KF_B_MODE_PROBS_287_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_OFFSET	(0x092C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_72, KF_B_MODE_PROBS_288
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_288_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_288_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_288_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_288_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_72, KF_B_MODE_PROBS_289
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_289_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_289_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_289_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_289_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_72, KF_B_MODE_PROBS_290
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_290_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_290_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_290_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_290_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_72, KF_B_MODE_PROBS_291
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_291_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_291_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_291_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_72_KF_B_MODE_PROBS_291_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_OFFSET	(0x0930)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_73, KF_B_MODE_PROBS_292
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_292_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_292_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_292_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_292_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_73, KF_B_MODE_PROBS_293
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_293_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_293_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_293_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_293_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_73, KF_B_MODE_PROBS_294
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_294_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_294_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_294_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_294_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_73, KF_B_MODE_PROBS_295
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_295_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_295_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_295_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_73_KF_B_MODE_PROBS_295_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_OFFSET	(0x0934)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_74, KF_B_MODE_PROBS_296
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_296_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_296_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_296_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_296_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_74, KF_B_MODE_PROBS_297
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_297_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_297_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_297_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_297_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_74, KF_B_MODE_PROBS_298
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_298_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_298_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_298_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_298_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_74, KF_B_MODE_PROBS_299
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_299_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_299_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_299_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_74_KF_B_MODE_PROBS_299_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_OFFSET	(0x0938)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_75, KF_B_MODE_PROBS_300
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_300_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_300_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_300_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_300_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_75, KF_B_MODE_PROBS_301
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_301_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_301_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_301_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_301_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_75, KF_B_MODE_PROBS_302
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_302_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_302_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_302_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_302_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_75, KF_B_MODE_PROBS_303
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_303_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_303_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_303_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_75_KF_B_MODE_PROBS_303_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_OFFSET	(0x093C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_76, KF_B_MODE_PROBS_304
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_304_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_304_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_304_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_304_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_76, KF_B_MODE_PROBS_305
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_305_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_305_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_305_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_305_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_76, KF_B_MODE_PROBS_306
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_306_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_306_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_306_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_306_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_76, KF_B_MODE_PROBS_307
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_307_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_307_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_307_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_76_KF_B_MODE_PROBS_307_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_OFFSET	(0x0940)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_77, KF_B_MODE_PROBS_308
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_308_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_308_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_308_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_308_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_77, KF_B_MODE_PROBS_309
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_309_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_309_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_309_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_309_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_77, KF_B_MODE_PROBS_310
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_310_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_310_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_310_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_310_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_77, KF_B_MODE_PROBS_311
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_311_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_311_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_311_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_77_KF_B_MODE_PROBS_311_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_OFFSET	(0x0944)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_78, KF_B_MODE_PROBS_312
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_312_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_312_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_312_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_312_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_78, KF_B_MODE_PROBS_313
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_313_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_313_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_313_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_313_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_78, KF_B_MODE_PROBS_314
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_314_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_314_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_314_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_314_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_78, KF_B_MODE_PROBS_315
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_315_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_315_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_315_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_78_KF_B_MODE_PROBS_315_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_OFFSET	(0x0948)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_79, KF_B_MODE_PROBS_316
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_316_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_316_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_316_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_316_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_79, KF_B_MODE_PROBS_317
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_317_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_317_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_317_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_317_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_79, KF_B_MODE_PROBS_318
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_318_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_318_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_318_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_318_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_79, KF_B_MODE_PROBS_319
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_319_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_319_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_319_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_79_KF_B_MODE_PROBS_319_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_OFFSET	(0x094C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_80, KF_B_MODE_PROBS_320
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_320_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_320_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_320_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_320_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_80, KF_B_MODE_PROBS_321
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_321_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_321_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_321_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_321_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_80, KF_B_MODE_PROBS_322
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_322_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_322_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_322_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_322_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_80, KF_B_MODE_PROBS_323
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_323_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_323_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_323_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_80_KF_B_MODE_PROBS_323_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_OFFSET	(0x0950)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_81, KF_B_MODE_PROBS_324
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_324_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_324_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_324_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_324_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_81, KF_B_MODE_PROBS_325
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_325_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_325_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_325_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_325_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_81, KF_B_MODE_PROBS_326
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_326_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_326_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_326_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_326_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_81, KF_B_MODE_PROBS_327
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_327_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_327_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_327_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_81_KF_B_MODE_PROBS_327_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_OFFSET	(0x0954)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_82, KF_B_MODE_PROBS_328
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_328_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_328_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_328_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_328_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_82, KF_B_MODE_PROBS_329
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_329_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_329_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_329_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_329_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_82, KF_B_MODE_PROBS_330
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_330_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_330_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_330_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_330_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_82, KF_B_MODE_PROBS_331
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_331_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_331_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_331_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_82_KF_B_MODE_PROBS_331_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_OFFSET	(0x0958)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_83, KF_B_MODE_PROBS_332
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_332_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_332_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_332_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_332_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_83, KF_B_MODE_PROBS_333
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_333_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_333_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_333_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_333_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_83, KF_B_MODE_PROBS_334
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_334_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_334_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_334_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_334_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_83, KF_B_MODE_PROBS_335
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_335_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_335_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_335_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_83_KF_B_MODE_PROBS_335_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_OFFSET	(0x095C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_84, KF_B_MODE_PROBS_336
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_336_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_336_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_336_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_336_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_84, KF_B_MODE_PROBS_337
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_337_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_337_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_337_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_337_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_84, KF_B_MODE_PROBS_338
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_338_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_338_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_338_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_338_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_84, KF_B_MODE_PROBS_339
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_339_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_339_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_339_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_84_KF_B_MODE_PROBS_339_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_OFFSET	(0x0960)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_85, KF_B_MODE_PROBS_340
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_340_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_340_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_340_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_340_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_85, KF_B_MODE_PROBS_341
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_341_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_341_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_341_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_341_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_85, KF_B_MODE_PROBS_342
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_342_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_342_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_342_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_342_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_85, KF_B_MODE_PROBS_343
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_343_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_343_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_343_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_85_KF_B_MODE_PROBS_343_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_OFFSET	(0x0964)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_86, KF_B_MODE_PROBS_344
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_344_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_344_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_344_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_344_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_86, KF_B_MODE_PROBS_345
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_345_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_345_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_345_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_345_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_86, KF_B_MODE_PROBS_346
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_346_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_346_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_346_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_346_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_86, KF_B_MODE_PROBS_347
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_347_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_347_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_347_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_86_KF_B_MODE_PROBS_347_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_OFFSET	(0x0968)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_87, KF_B_MODE_PROBS_348
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_348_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_348_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_348_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_348_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_87, KF_B_MODE_PROBS_349
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_349_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_349_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_349_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_349_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_87, KF_B_MODE_PROBS_350
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_350_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_350_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_350_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_350_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_87, KF_B_MODE_PROBS_351
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_351_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_351_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_351_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_87_KF_B_MODE_PROBS_351_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_OFFSET	(0x096C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_88, KF_B_MODE_PROBS_352
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_352_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_352_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_352_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_352_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_88, KF_B_MODE_PROBS_353
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_353_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_353_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_353_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_353_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_88, KF_B_MODE_PROBS_354
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_354_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_354_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_354_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_354_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_88, KF_B_MODE_PROBS_355
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_355_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_355_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_355_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_88_KF_B_MODE_PROBS_355_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_OFFSET	(0x0970)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_89, KF_B_MODE_PROBS_356
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_356_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_356_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_356_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_356_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_89, KF_B_MODE_PROBS_357
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_357_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_357_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_357_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_357_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_89, KF_B_MODE_PROBS_358
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_358_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_358_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_358_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_358_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_89, KF_B_MODE_PROBS_359
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_359_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_359_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_359_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_89_KF_B_MODE_PROBS_359_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_OFFSET	(0x0974)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_90, KF_B_MODE_PROBS_360
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_360_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_360_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_360_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_360_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_90, KF_B_MODE_PROBS_361
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_361_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_361_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_361_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_361_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_90, KF_B_MODE_PROBS_362
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_362_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_362_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_362_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_362_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_90, KF_B_MODE_PROBS_363
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_363_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_363_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_363_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_90_KF_B_MODE_PROBS_363_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_OFFSET	(0x0978)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_91, KF_B_MODE_PROBS_364
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_364_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_364_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_364_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_364_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_91, KF_B_MODE_PROBS_365
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_365_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_365_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_365_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_365_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_91, KF_B_MODE_PROBS_366
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_366_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_366_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_366_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_366_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_91, KF_B_MODE_PROBS_367
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_367_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_367_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_367_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_91_KF_B_MODE_PROBS_367_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_OFFSET	(0x097C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_92, KF_B_MODE_PROBS_368
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_368_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_368_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_368_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_368_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_92, KF_B_MODE_PROBS_369
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_369_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_369_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_369_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_369_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_92, KF_B_MODE_PROBS_370
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_370_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_370_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_370_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_370_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_92, KF_B_MODE_PROBS_371
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_371_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_371_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_371_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_92_KF_B_MODE_PROBS_371_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_OFFSET	(0x0980)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_93, KF_B_MODE_PROBS_372
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_372_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_372_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_372_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_372_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_93, KF_B_MODE_PROBS_373
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_373_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_373_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_373_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_373_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_93, KF_B_MODE_PROBS_374
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_374_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_374_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_374_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_374_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_93, KF_B_MODE_PROBS_375
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_375_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_375_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_375_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_93_KF_B_MODE_PROBS_375_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_OFFSET	(0x0984)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_94, KF_B_MODE_PROBS_376
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_376_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_376_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_376_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_376_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_94, KF_B_MODE_PROBS_377
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_377_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_377_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_377_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_377_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_94, KF_B_MODE_PROBS_378
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_378_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_378_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_378_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_378_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_94, KF_B_MODE_PROBS_379
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_379_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_379_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_379_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_94_KF_B_MODE_PROBS_379_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_OFFSET	(0x0988)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_95, KF_B_MODE_PROBS_380
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_380_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_380_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_380_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_380_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_95, KF_B_MODE_PROBS_381
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_381_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_381_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_381_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_381_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_95, KF_B_MODE_PROBS_382
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_382_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_382_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_382_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_382_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_95, KF_B_MODE_PROBS_383
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_383_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_383_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_383_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_95_KF_B_MODE_PROBS_383_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_OFFSET	(0x098C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_96, KF_B_MODE_PROBS_384
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_384_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_384_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_384_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_384_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_96, KF_B_MODE_PROBS_385
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_385_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_385_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_385_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_385_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_96, KF_B_MODE_PROBS_386
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_386_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_386_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_386_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_386_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_96, KF_B_MODE_PROBS_387
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_387_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_387_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_387_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_96_KF_B_MODE_PROBS_387_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_OFFSET	(0x0990)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_97, KF_B_MODE_PROBS_388
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_388_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_388_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_388_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_388_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_97, KF_B_MODE_PROBS_389
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_389_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_389_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_389_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_389_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_97, KF_B_MODE_PROBS_390
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_390_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_390_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_390_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_390_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_97, KF_B_MODE_PROBS_391
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_391_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_391_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_391_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_97_KF_B_MODE_PROBS_391_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_OFFSET	(0x0994)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_98, KF_B_MODE_PROBS_392
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_392_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_392_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_392_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_392_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_98, KF_B_MODE_PROBS_393
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_393_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_393_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_393_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_393_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_98, KF_B_MODE_PROBS_394
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_394_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_394_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_394_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_394_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_98, KF_B_MODE_PROBS_395
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_395_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_395_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_395_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_98_KF_B_MODE_PROBS_395_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_OFFSET	(0x0998)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_99, KF_B_MODE_PROBS_396
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_396_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_396_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_396_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_396_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_99, KF_B_MODE_PROBS_397
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_397_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_397_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_397_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_397_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_99, KF_B_MODE_PROBS_398
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_398_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_398_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_398_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_398_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_99, KF_B_MODE_PROBS_399
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_399_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_399_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_399_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_99_KF_B_MODE_PROBS_399_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_OFFSET	(0x099C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_100, KF_B_MODE_PROBS_400
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_400_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_400_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_400_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_400_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_100, KF_B_MODE_PROBS_401
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_401_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_401_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_401_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_401_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_100, KF_B_MODE_PROBS_402
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_402_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_402_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_402_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_402_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_100, KF_B_MODE_PROBS_403
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_403_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_403_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_403_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_100_KF_B_MODE_PROBS_403_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_OFFSET	(0x09A0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_101, KF_B_MODE_PROBS_404
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_404_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_404_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_404_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_404_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_101, KF_B_MODE_PROBS_405
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_405_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_405_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_405_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_405_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_101, KF_B_MODE_PROBS_406
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_406_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_406_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_406_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_406_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_101, KF_B_MODE_PROBS_407
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_407_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_407_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_407_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_101_KF_B_MODE_PROBS_407_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_OFFSET	(0x09A4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_102, KF_B_MODE_PROBS_408
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_408_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_408_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_408_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_408_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_102, KF_B_MODE_PROBS_409
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_409_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_409_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_409_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_409_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_102, KF_B_MODE_PROBS_410
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_410_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_410_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_410_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_410_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_102, KF_B_MODE_PROBS_411
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_411_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_411_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_411_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_102_KF_B_MODE_PROBS_411_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_OFFSET	(0x09A8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_103, KF_B_MODE_PROBS_412
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_412_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_412_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_412_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_412_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_103, KF_B_MODE_PROBS_413
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_413_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_413_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_413_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_413_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_103, KF_B_MODE_PROBS_414
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_414_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_414_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_414_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_414_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_103, KF_B_MODE_PROBS_415
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_415_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_415_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_415_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_103_KF_B_MODE_PROBS_415_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_OFFSET	(0x09AC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_104, KF_B_MODE_PROBS_416
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_416_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_416_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_416_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_416_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_104, KF_B_MODE_PROBS_417
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_417_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_417_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_417_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_417_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_104, KF_B_MODE_PROBS_418
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_418_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_418_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_418_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_418_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_104, KF_B_MODE_PROBS_419
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_419_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_419_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_419_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_104_KF_B_MODE_PROBS_419_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_OFFSET	(0x09B0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_105, KF_B_MODE_PROBS_420
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_420_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_420_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_420_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_420_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_105, KF_B_MODE_PROBS_421
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_421_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_421_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_421_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_421_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_105, KF_B_MODE_PROBS_422
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_422_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_422_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_422_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_422_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_105, KF_B_MODE_PROBS_423
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_423_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_423_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_423_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_105_KF_B_MODE_PROBS_423_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_OFFSET	(0x09B4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_106, KF_B_MODE_PROBS_424
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_424_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_424_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_424_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_424_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_106, KF_B_MODE_PROBS_425
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_425_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_425_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_425_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_425_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_106, KF_B_MODE_PROBS_426
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_426_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_426_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_426_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_426_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_106, KF_B_MODE_PROBS_427
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_427_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_427_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_427_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_106_KF_B_MODE_PROBS_427_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_OFFSET	(0x09B8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_107, KF_B_MODE_PROBS_428
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_428_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_428_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_428_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_428_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_107, KF_B_MODE_PROBS_429
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_429_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_429_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_429_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_429_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_107, KF_B_MODE_PROBS_430
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_430_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_430_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_430_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_430_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_107, KF_B_MODE_PROBS_431
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_431_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_431_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_431_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_107_KF_B_MODE_PROBS_431_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_OFFSET	(0x09BC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_108, KF_B_MODE_PROBS_432
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_432_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_432_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_432_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_432_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_108, KF_B_MODE_PROBS_433
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_433_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_433_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_433_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_433_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_108, KF_B_MODE_PROBS_434
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_434_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_434_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_434_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_434_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_108, KF_B_MODE_PROBS_435
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_435_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_435_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_435_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_108_KF_B_MODE_PROBS_435_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_OFFSET	(0x09C0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_109, KF_B_MODE_PROBS_436
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_436_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_436_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_436_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_436_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_109, KF_B_MODE_PROBS_437
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_437_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_437_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_437_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_437_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_109, KF_B_MODE_PROBS_438
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_438_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_438_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_438_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_438_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_109, KF_B_MODE_PROBS_439
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_439_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_439_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_439_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_109_KF_B_MODE_PROBS_439_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_OFFSET	(0x09C4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_110, KF_B_MODE_PROBS_440
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_440_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_440_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_440_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_440_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_110, KF_B_MODE_PROBS_441
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_441_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_441_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_441_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_441_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_110, KF_B_MODE_PROBS_442
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_442_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_442_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_442_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_442_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_110, KF_B_MODE_PROBS_443
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_443_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_443_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_443_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_110_KF_B_MODE_PROBS_443_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_OFFSET	(0x09C8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_111, KF_B_MODE_PROBS_444
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_444_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_444_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_444_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_444_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_111, KF_B_MODE_PROBS_445
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_445_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_445_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_445_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_445_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_111, KF_B_MODE_PROBS_446
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_446_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_446_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_446_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_446_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_111, KF_B_MODE_PROBS_447
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_447_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_447_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_447_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_111_KF_B_MODE_PROBS_447_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_OFFSET	(0x09CC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_112, KF_B_MODE_PROBS_448
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_448_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_448_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_448_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_448_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_112, KF_B_MODE_PROBS_449
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_449_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_449_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_449_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_449_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_112, KF_B_MODE_PROBS_450
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_450_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_450_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_450_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_450_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_112, KF_B_MODE_PROBS_451
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_451_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_451_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_451_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_112_KF_B_MODE_PROBS_451_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_OFFSET	(0x09D0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_113, KF_B_MODE_PROBS_452
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_452_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_452_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_452_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_452_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_113, KF_B_MODE_PROBS_453
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_453_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_453_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_453_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_453_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_113, KF_B_MODE_PROBS_454
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_454_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_454_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_454_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_454_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_113, KF_B_MODE_PROBS_455
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_455_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_455_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_455_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_113_KF_B_MODE_PROBS_455_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_OFFSET	(0x09D4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_114, KF_B_MODE_PROBS_456
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_456_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_456_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_456_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_456_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_114, KF_B_MODE_PROBS_457
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_457_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_457_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_457_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_457_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_114, KF_B_MODE_PROBS_458
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_458_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_458_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_458_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_458_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_114, KF_B_MODE_PROBS_459
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_459_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_459_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_459_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_114_KF_B_MODE_PROBS_459_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_OFFSET	(0x09D8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_115, KF_B_MODE_PROBS_460
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_460_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_460_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_460_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_460_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_115, KF_B_MODE_PROBS_461
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_461_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_461_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_461_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_461_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_115, KF_B_MODE_PROBS_462
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_462_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_462_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_462_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_462_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_115, KF_B_MODE_PROBS_463
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_463_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_463_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_463_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_115_KF_B_MODE_PROBS_463_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_OFFSET	(0x09DC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_116, KF_B_MODE_PROBS_464
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_464_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_464_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_464_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_464_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_116, KF_B_MODE_PROBS_465
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_465_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_465_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_465_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_465_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_116, KF_B_MODE_PROBS_466
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_466_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_466_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_466_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_466_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_116, KF_B_MODE_PROBS_467
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_467_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_467_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_467_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_116_KF_B_MODE_PROBS_467_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_OFFSET	(0x09E0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_117, KF_B_MODE_PROBS_468
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_468_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_468_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_468_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_468_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_117, KF_B_MODE_PROBS_469
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_469_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_469_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_469_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_469_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_117, KF_B_MODE_PROBS_470
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_470_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_470_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_470_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_470_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_117, KF_B_MODE_PROBS_471
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_471_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_471_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_471_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_117_KF_B_MODE_PROBS_471_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_OFFSET	(0x09E4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_118, KF_B_MODE_PROBS_472
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_472_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_472_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_472_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_472_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_118, KF_B_MODE_PROBS_473
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_473_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_473_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_473_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_473_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_118, KF_B_MODE_PROBS_474
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_474_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_474_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_474_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_474_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_118, KF_B_MODE_PROBS_475
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_475_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_475_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_475_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_118_KF_B_MODE_PROBS_475_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_OFFSET	(0x09E8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_119, KF_B_MODE_PROBS_476
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_476_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_476_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_476_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_476_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_119, KF_B_MODE_PROBS_477
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_477_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_477_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_477_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_477_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_119, KF_B_MODE_PROBS_478
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_478_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_478_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_478_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_478_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_119, KF_B_MODE_PROBS_479
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_479_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_479_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_479_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_119_KF_B_MODE_PROBS_479_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_OFFSET	(0x09EC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_120, KF_B_MODE_PROBS_480
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_480_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_480_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_480_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_480_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_120, KF_B_MODE_PROBS_481
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_481_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_481_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_481_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_481_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_120, KF_B_MODE_PROBS_482
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_482_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_482_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_482_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_482_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_120, KF_B_MODE_PROBS_483
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_483_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_483_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_483_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_120_KF_B_MODE_PROBS_483_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_OFFSET	(0x09F0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_121, KF_B_MODE_PROBS_484
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_484_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_484_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_484_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_484_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_121, KF_B_MODE_PROBS_485
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_485_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_485_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_485_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_485_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_121, KF_B_MODE_PROBS_486
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_486_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_486_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_486_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_486_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_121, KF_B_MODE_PROBS_487
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_487_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_487_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_487_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_121_KF_B_MODE_PROBS_487_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_OFFSET	(0x09F4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_122, KF_B_MODE_PROBS_488
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_488_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_488_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_488_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_488_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_122, KF_B_MODE_PROBS_489
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_489_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_489_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_489_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_489_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_122, KF_B_MODE_PROBS_490
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_490_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_490_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_490_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_490_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_122, KF_B_MODE_PROBS_491
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_491_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_491_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_491_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_122_KF_B_MODE_PROBS_491_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_OFFSET	(0x09F8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_123, KF_B_MODE_PROBS_492
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_492_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_492_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_492_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_492_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_123, KF_B_MODE_PROBS_493
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_493_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_493_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_493_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_493_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_123, KF_B_MODE_PROBS_494
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_494_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_494_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_494_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_494_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_123, KF_B_MODE_PROBS_495
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_495_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_495_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_495_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_123_KF_B_MODE_PROBS_495_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_OFFSET	(0x09FC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_124, KF_B_MODE_PROBS_496
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_496_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_496_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_496_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_496_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_124, KF_B_MODE_PROBS_497
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_497_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_497_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_497_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_497_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_124, KF_B_MODE_PROBS_498
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_498_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_498_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_498_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_498_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_124, KF_B_MODE_PROBS_499
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_499_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_499_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_499_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_124_KF_B_MODE_PROBS_499_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_OFFSET	(0x0A00)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_125, KF_B_MODE_PROBS_500
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_500_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_500_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_500_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_500_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_125, KF_B_MODE_PROBS_501
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_501_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_501_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_501_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_501_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_125, KF_B_MODE_PROBS_502
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_502_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_502_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_502_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_502_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_125, KF_B_MODE_PROBS_503
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_503_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_503_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_503_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_125_KF_B_MODE_PROBS_503_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_OFFSET	(0x0A04)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_126, KF_B_MODE_PROBS_504
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_504_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_504_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_504_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_504_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_126, KF_B_MODE_PROBS_505
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_505_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_505_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_505_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_505_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_126, KF_B_MODE_PROBS_506
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_506_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_506_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_506_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_506_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_126, KF_B_MODE_PROBS_507
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_507_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_507_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_507_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_126_KF_B_MODE_PROBS_507_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_OFFSET	(0x0A08)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_127, KF_B_MODE_PROBS_508
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_508_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_508_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_508_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_508_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_127, KF_B_MODE_PROBS_509
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_509_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_509_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_509_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_509_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_127, KF_B_MODE_PROBS_510
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_510_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_510_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_510_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_510_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_127, KF_B_MODE_PROBS_511
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_511_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_511_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_511_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_127_KF_B_MODE_PROBS_511_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_OFFSET	(0x0A0C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_128, KF_B_MODE_PROBS_512
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_512_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_512_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_512_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_512_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_128, KF_B_MODE_PROBS_513
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_513_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_513_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_513_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_513_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_128, KF_B_MODE_PROBS_514
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_514_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_514_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_514_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_514_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_128, KF_B_MODE_PROBS_515
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_515_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_515_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_515_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_128_KF_B_MODE_PROBS_515_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_OFFSET	(0x0A10)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_129, KF_B_MODE_PROBS_516
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_516_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_516_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_516_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_516_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_129, KF_B_MODE_PROBS_517
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_517_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_517_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_517_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_517_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_129, KF_B_MODE_PROBS_518
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_518_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_518_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_518_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_518_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_129, KF_B_MODE_PROBS_519
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_519_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_519_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_519_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_129_KF_B_MODE_PROBS_519_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_OFFSET	(0x0A14)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_130, KF_B_MODE_PROBS_520
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_520_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_520_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_520_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_520_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_130, KF_B_MODE_PROBS_521
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_521_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_521_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_521_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_521_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_130, KF_B_MODE_PROBS_522
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_522_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_522_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_522_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_522_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_130, KF_B_MODE_PROBS_523
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_523_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_523_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_523_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_130_KF_B_MODE_PROBS_523_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_OFFSET	(0x0A18)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_131, KF_B_MODE_PROBS_524
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_524_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_524_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_524_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_524_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_131, KF_B_MODE_PROBS_525
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_525_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_525_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_525_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_525_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_131, KF_B_MODE_PROBS_526
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_526_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_526_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_526_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_526_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_131, KF_B_MODE_PROBS_527
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_527_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_527_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_527_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_131_KF_B_MODE_PROBS_527_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_OFFSET	(0x0A1C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_132, KF_B_MODE_PROBS_528
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_528_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_528_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_528_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_528_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_132, KF_B_MODE_PROBS_529
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_529_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_529_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_529_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_529_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_132, KF_B_MODE_PROBS_530
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_530_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_530_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_530_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_530_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_132, KF_B_MODE_PROBS_531
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_531_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_531_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_531_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_132_KF_B_MODE_PROBS_531_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_OFFSET	(0x0A20)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_133, KF_B_MODE_PROBS_532
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_532_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_532_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_532_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_532_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_133, KF_B_MODE_PROBS_533
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_533_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_533_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_533_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_533_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_133, KF_B_MODE_PROBS_534
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_534_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_534_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_534_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_534_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_133, KF_B_MODE_PROBS_535
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_535_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_535_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_535_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_133_KF_B_MODE_PROBS_535_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_OFFSET	(0x0A24)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_134, KF_B_MODE_PROBS_536
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_536_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_536_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_536_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_536_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_134, KF_B_MODE_PROBS_537
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_537_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_537_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_537_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_537_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_134, KF_B_MODE_PROBS_538
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_538_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_538_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_538_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_538_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_134, KF_B_MODE_PROBS_539
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_539_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_539_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_539_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_134_KF_B_MODE_PROBS_539_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_OFFSET	(0x0A28)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_135, KF_B_MODE_PROBS_540
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_540_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_540_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_540_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_540_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_135, KF_B_MODE_PROBS_541
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_541_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_541_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_541_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_541_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_135, KF_B_MODE_PROBS_542
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_542_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_542_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_542_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_542_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_135, KF_B_MODE_PROBS_543
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_543_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_543_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_543_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_135_KF_B_MODE_PROBS_543_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_OFFSET	(0x0A2C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_136, KF_B_MODE_PROBS_544
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_544_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_544_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_544_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_544_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_136, KF_B_MODE_PROBS_545
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_545_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_545_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_545_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_545_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_136, KF_B_MODE_PROBS_546
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_546_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_546_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_546_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_546_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_136, KF_B_MODE_PROBS_547
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_547_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_547_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_547_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_136_KF_B_MODE_PROBS_547_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_OFFSET	(0x0A30)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_137, KF_B_MODE_PROBS_548
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_548_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_548_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_548_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_548_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_137, KF_B_MODE_PROBS_549
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_549_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_549_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_549_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_549_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_137, KF_B_MODE_PROBS_550
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_550_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_550_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_550_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_550_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_137, KF_B_MODE_PROBS_551
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_551_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_551_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_551_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_137_KF_B_MODE_PROBS_551_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_OFFSET	(0x0A34)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_138, KF_B_MODE_PROBS_552
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_552_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_552_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_552_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_552_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_138, KF_B_MODE_PROBS_553
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_553_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_553_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_553_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_553_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_138, KF_B_MODE_PROBS_554
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_554_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_554_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_554_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_554_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_138, KF_B_MODE_PROBS_555
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_555_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_555_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_555_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_138_KF_B_MODE_PROBS_555_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_OFFSET	(0x0A38)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_139, KF_B_MODE_PROBS_556
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_556_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_556_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_556_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_556_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_139, KF_B_MODE_PROBS_557
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_557_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_557_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_557_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_557_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_139, KF_B_MODE_PROBS_558
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_558_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_558_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_558_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_558_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_139, KF_B_MODE_PROBS_559
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_559_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_559_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_559_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_139_KF_B_MODE_PROBS_559_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_OFFSET	(0x0A3C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_140, KF_B_MODE_PROBS_560
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_560_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_560_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_560_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_560_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_140, KF_B_MODE_PROBS_561
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_561_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_561_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_561_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_561_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_140, KF_B_MODE_PROBS_562
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_562_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_562_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_562_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_562_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_140, KF_B_MODE_PROBS_563
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_563_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_563_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_563_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_140_KF_B_MODE_PROBS_563_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_OFFSET	(0x0A40)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_141, KF_B_MODE_PROBS_564
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_564_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_564_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_564_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_564_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_141, KF_B_MODE_PROBS_565
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_565_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_565_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_565_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_565_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_141, KF_B_MODE_PROBS_566
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_566_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_566_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_566_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_566_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_141, KF_B_MODE_PROBS_567
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_567_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_567_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_567_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_141_KF_B_MODE_PROBS_567_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_OFFSET	(0x0A44)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_142, KF_B_MODE_PROBS_568
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_568_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_568_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_568_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_568_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_142, KF_B_MODE_PROBS_569
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_569_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_569_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_569_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_569_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_142, KF_B_MODE_PROBS_570
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_570_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_570_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_570_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_570_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_142, KF_B_MODE_PROBS_571
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_571_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_571_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_571_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_142_KF_B_MODE_PROBS_571_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_OFFSET	(0x0A48)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_143, KF_B_MODE_PROBS_572
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_572_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_572_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_572_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_572_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_143, KF_B_MODE_PROBS_573
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_573_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_573_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_573_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_573_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_143, KF_B_MODE_PROBS_574
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_574_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_574_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_574_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_574_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_143, KF_B_MODE_PROBS_575
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_575_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_575_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_575_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_143_KF_B_MODE_PROBS_575_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_OFFSET	(0x0A4C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_144, KF_B_MODE_PROBS_576
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_576_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_576_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_576_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_576_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_144, KF_B_MODE_PROBS_577
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_577_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_577_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_577_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_577_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_144, KF_B_MODE_PROBS_578
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_578_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_578_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_578_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_578_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_144, KF_B_MODE_PROBS_579
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_579_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_579_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_579_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_144_KF_B_MODE_PROBS_579_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_OFFSET	(0x0A50)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_145, KF_B_MODE_PROBS_580
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_580_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_580_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_580_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_580_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_145, KF_B_MODE_PROBS_581
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_581_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_581_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_581_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_581_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_145, KF_B_MODE_PROBS_582
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_582_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_582_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_582_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_582_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_145, KF_B_MODE_PROBS_583
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_583_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_583_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_583_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_145_KF_B_MODE_PROBS_583_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_OFFSET	(0x0A54)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_146, KF_B_MODE_PROBS_584
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_584_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_584_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_584_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_584_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_146, KF_B_MODE_PROBS_585
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_585_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_585_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_585_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_585_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_146, KF_B_MODE_PROBS_586
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_586_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_586_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_586_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_586_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_146, KF_B_MODE_PROBS_587
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_587_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_587_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_587_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_146_KF_B_MODE_PROBS_587_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_OFFSET	(0x0A58)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_147, KF_B_MODE_PROBS_588
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_588_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_588_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_588_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_588_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_147, KF_B_MODE_PROBS_589
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_589_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_589_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_589_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_589_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_147, KF_B_MODE_PROBS_590
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_590_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_590_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_590_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_590_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_147, KF_B_MODE_PROBS_591
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_591_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_591_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_591_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_147_KF_B_MODE_PROBS_591_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_OFFSET	(0x0A5C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_148, KF_B_MODE_PROBS_592
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_592_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_592_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_592_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_592_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_148, KF_B_MODE_PROBS_593
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_593_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_593_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_593_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_593_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_148, KF_B_MODE_PROBS_594
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_594_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_594_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_594_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_594_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_148, KF_B_MODE_PROBS_595
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_595_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_595_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_595_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_148_KF_B_MODE_PROBS_595_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_OFFSET	(0x0A60)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_149, KF_B_MODE_PROBS_596
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_596_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_596_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_596_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_596_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_149, KF_B_MODE_PROBS_597
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_597_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_597_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_597_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_597_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_149, KF_B_MODE_PROBS_598
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_598_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_598_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_598_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_598_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_149, KF_B_MODE_PROBS_599
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_599_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_599_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_599_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_149_KF_B_MODE_PROBS_599_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_OFFSET	(0x0A64)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_150, KF_B_MODE_PROBS_600
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_600_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_600_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_600_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_600_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_150, KF_B_MODE_PROBS_601
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_601_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_601_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_601_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_601_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_150, KF_B_MODE_PROBS_602
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_602_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_602_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_602_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_602_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_150, KF_B_MODE_PROBS_603
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_603_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_603_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_603_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_150_KF_B_MODE_PROBS_603_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_OFFSET	(0x0A68)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_151, KF_B_MODE_PROBS_604
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_604_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_604_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_604_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_604_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_151, KF_B_MODE_PROBS_605
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_605_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_605_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_605_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_605_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_151, KF_B_MODE_PROBS_606
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_606_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_606_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_606_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_606_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_151, KF_B_MODE_PROBS_607
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_607_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_607_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_607_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_151_KF_B_MODE_PROBS_607_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_OFFSET	(0x0A6C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_152, KF_B_MODE_PROBS_608
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_608_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_608_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_608_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_608_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_152, KF_B_MODE_PROBS_609
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_609_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_609_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_609_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_609_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_152, KF_B_MODE_PROBS_610
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_610_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_610_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_610_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_610_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_152, KF_B_MODE_PROBS_611
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_611_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_611_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_611_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_152_KF_B_MODE_PROBS_611_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_OFFSET	(0x0A70)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_153, KF_B_MODE_PROBS_612
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_612_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_612_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_612_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_612_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_153, KF_B_MODE_PROBS_613
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_613_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_613_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_613_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_613_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_153, KF_B_MODE_PROBS_614
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_614_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_614_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_614_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_614_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_153, KF_B_MODE_PROBS_615
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_615_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_615_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_615_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_153_KF_B_MODE_PROBS_615_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_OFFSET	(0x0A74)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_154, KF_B_MODE_PROBS_616
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_616_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_616_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_616_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_616_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_154, KF_B_MODE_PROBS_617
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_617_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_617_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_617_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_617_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_154, KF_B_MODE_PROBS_618
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_618_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_618_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_618_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_618_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_154, KF_B_MODE_PROBS_619
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_619_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_619_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_619_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_154_KF_B_MODE_PROBS_619_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_OFFSET	(0x0A78)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_155, KF_B_MODE_PROBS_620
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_620_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_620_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_620_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_620_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_155, KF_B_MODE_PROBS_621
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_621_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_621_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_621_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_621_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_155, KF_B_MODE_PROBS_622
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_622_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_622_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_622_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_622_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_155, KF_B_MODE_PROBS_623
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_623_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_623_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_623_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_155_KF_B_MODE_PROBS_623_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_OFFSET	(0x0A7C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_156, KF_B_MODE_PROBS_624
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_624_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_624_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_624_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_624_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_156, KF_B_MODE_PROBS_625
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_625_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_625_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_625_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_625_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_156, KF_B_MODE_PROBS_626
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_626_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_626_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_626_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_626_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_156, KF_B_MODE_PROBS_627
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_627_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_627_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_627_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_156_KF_B_MODE_PROBS_627_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_OFFSET	(0x0A80)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_157, KF_B_MODE_PROBS_628
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_628_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_628_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_628_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_628_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_157, KF_B_MODE_PROBS_629
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_629_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_629_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_629_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_629_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_157, KF_B_MODE_PROBS_630
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_630_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_630_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_630_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_630_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_157, KF_B_MODE_PROBS_631
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_631_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_631_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_631_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_157_KF_B_MODE_PROBS_631_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_OFFSET	(0x0A84)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_158, KF_B_MODE_PROBS_632
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_632_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_632_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_632_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_632_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_158, KF_B_MODE_PROBS_633
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_633_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_633_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_633_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_633_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_158, KF_B_MODE_PROBS_634
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_634_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_634_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_634_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_634_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_158, KF_B_MODE_PROBS_635
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_635_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_635_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_635_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_158_KF_B_MODE_PROBS_635_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_OFFSET	(0x0A88)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_159, KF_B_MODE_PROBS_636
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_636_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_636_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_636_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_636_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_159, KF_B_MODE_PROBS_637
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_637_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_637_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_637_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_637_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_159, KF_B_MODE_PROBS_638
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_638_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_638_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_638_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_638_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_159, KF_B_MODE_PROBS_639
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_639_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_639_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_639_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_159_KF_B_MODE_PROBS_639_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_OFFSET	(0x0A8C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_160, KF_B_MODE_PROBS_640
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_640_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_640_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_640_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_640_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_160, KF_B_MODE_PROBS_641
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_641_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_641_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_641_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_641_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_160, KF_B_MODE_PROBS_642
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_642_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_642_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_642_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_642_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_160, KF_B_MODE_PROBS_643
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_643_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_643_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_643_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_160_KF_B_MODE_PROBS_643_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_OFFSET	(0x0A90)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_161, KF_B_MODE_PROBS_644
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_644_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_644_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_644_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_644_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_161, KF_B_MODE_PROBS_645
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_645_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_645_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_645_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_645_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_161, KF_B_MODE_PROBS_646
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_646_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_646_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_646_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_646_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_161, KF_B_MODE_PROBS_647
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_647_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_647_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_647_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_161_KF_B_MODE_PROBS_647_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_OFFSET	(0x0A94)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_162, KF_B_MODE_PROBS_648
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_648_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_648_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_648_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_648_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_162, KF_B_MODE_PROBS_649
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_649_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_649_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_649_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_649_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_162, KF_B_MODE_PROBS_650
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_650_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_650_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_650_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_650_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_162, KF_B_MODE_PROBS_651
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_651_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_651_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_651_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_162_KF_B_MODE_PROBS_651_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_OFFSET	(0x0A98)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_163, KF_B_MODE_PROBS_652
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_652_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_652_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_652_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_652_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_163, KF_B_MODE_PROBS_653
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_653_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_653_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_653_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_653_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_163, KF_B_MODE_PROBS_654
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_654_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_654_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_654_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_654_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_163, KF_B_MODE_PROBS_655
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_655_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_655_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_655_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_163_KF_B_MODE_PROBS_655_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_OFFSET	(0x0A9C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_164, KF_B_MODE_PROBS_656
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_656_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_656_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_656_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_656_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_164, KF_B_MODE_PROBS_657
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_657_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_657_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_657_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_657_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_164, KF_B_MODE_PROBS_658
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_658_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_658_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_658_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_658_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_164, KF_B_MODE_PROBS_659
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_659_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_659_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_659_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_164_KF_B_MODE_PROBS_659_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_OFFSET	(0x0AA0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_165, KF_B_MODE_PROBS_660
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_660_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_660_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_660_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_660_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_165, KF_B_MODE_PROBS_661
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_661_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_661_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_661_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_661_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_165, KF_B_MODE_PROBS_662
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_662_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_662_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_662_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_662_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_165, KF_B_MODE_PROBS_663
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_663_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_663_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_663_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_165_KF_B_MODE_PROBS_663_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_OFFSET	(0x0AA4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_166, KF_B_MODE_PROBS_664
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_664_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_664_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_664_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_664_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_166, KF_B_MODE_PROBS_665
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_665_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_665_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_665_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_665_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_166, KF_B_MODE_PROBS_666
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_666_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_666_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_666_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_666_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_166, KF_B_MODE_PROBS_667
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_667_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_667_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_667_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_166_KF_B_MODE_PROBS_667_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_OFFSET	(0x0AA8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_167, KF_B_MODE_PROBS_668
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_668_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_668_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_668_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_668_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_167, KF_B_MODE_PROBS_669
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_669_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_669_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_669_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_669_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_167, KF_B_MODE_PROBS_670
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_670_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_670_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_670_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_670_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_167, KF_B_MODE_PROBS_671
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_671_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_671_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_671_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_167_KF_B_MODE_PROBS_671_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_OFFSET	(0x0AAC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_168, KF_B_MODE_PROBS_672
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_672_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_672_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_672_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_672_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_168, KF_B_MODE_PROBS_673
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_673_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_673_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_673_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_673_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_168, KF_B_MODE_PROBS_674
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_674_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_674_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_674_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_674_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_168, KF_B_MODE_PROBS_675
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_675_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_675_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_675_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_168_KF_B_MODE_PROBS_675_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_OFFSET	(0x0AB0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_169, KF_B_MODE_PROBS_676
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_676_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_676_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_676_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_676_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_169, KF_B_MODE_PROBS_677
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_677_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_677_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_677_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_677_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_169, KF_B_MODE_PROBS_678
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_678_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_678_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_678_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_678_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_169, KF_B_MODE_PROBS_679
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_679_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_679_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_679_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_169_KF_B_MODE_PROBS_679_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_OFFSET	(0x0AB4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_170, KF_B_MODE_PROBS_680
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_680_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_680_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_680_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_680_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_170, KF_B_MODE_PROBS_681
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_681_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_681_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_681_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_681_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_170, KF_B_MODE_PROBS_682
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_682_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_682_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_682_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_682_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_170, KF_B_MODE_PROBS_683
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_683_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_683_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_683_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_170_KF_B_MODE_PROBS_683_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_OFFSET	(0x0AB8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_171, KF_B_MODE_PROBS_684
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_684_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_684_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_684_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_684_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_171, KF_B_MODE_PROBS_685
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_685_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_685_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_685_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_685_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_171, KF_B_MODE_PROBS_686
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_686_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_686_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_686_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_686_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_171, KF_B_MODE_PROBS_687
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_687_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_687_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_687_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_171_KF_B_MODE_PROBS_687_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_OFFSET	(0x0ABC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_172, KF_B_MODE_PROBS_688
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_688_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_688_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_688_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_688_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_172, KF_B_MODE_PROBS_689
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_689_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_689_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_689_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_689_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_172, KF_B_MODE_PROBS_690
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_690_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_690_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_690_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_690_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_172, KF_B_MODE_PROBS_691
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_691_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_691_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_691_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_172_KF_B_MODE_PROBS_691_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_OFFSET	(0x0AC0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_173, KF_B_MODE_PROBS_692
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_692_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_692_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_692_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_692_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_173, KF_B_MODE_PROBS_693
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_693_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_693_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_693_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_693_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_173, KF_B_MODE_PROBS_694
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_694_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_694_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_694_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_694_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_173, KF_B_MODE_PROBS_695
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_695_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_695_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_695_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_173_KF_B_MODE_PROBS_695_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_OFFSET	(0x0AC4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_174, KF_B_MODE_PROBS_696
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_696_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_696_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_696_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_696_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_174, KF_B_MODE_PROBS_697
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_697_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_697_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_697_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_697_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_174, KF_B_MODE_PROBS_698
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_698_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_698_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_698_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_698_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_174, KF_B_MODE_PROBS_699
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_699_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_699_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_699_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_174_KF_B_MODE_PROBS_699_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_OFFSET	(0x0AC8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_175, KF_B_MODE_PROBS_700
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_700_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_700_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_700_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_700_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_175, KF_B_MODE_PROBS_701
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_701_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_701_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_701_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_701_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_175, KF_B_MODE_PROBS_702
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_702_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_702_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_702_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_702_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_175, KF_B_MODE_PROBS_703
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_703_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_703_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_703_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_175_KF_B_MODE_PROBS_703_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_OFFSET	(0x0ACC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_176, KF_B_MODE_PROBS_704
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_704_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_704_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_704_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_704_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_176, KF_B_MODE_PROBS_705
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_705_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_705_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_705_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_705_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_176, KF_B_MODE_PROBS_706
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_706_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_706_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_706_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_706_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_176, KF_B_MODE_PROBS_707
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_707_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_707_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_707_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_176_KF_B_MODE_PROBS_707_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_OFFSET	(0x0AD0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_177, KF_B_MODE_PROBS_708
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_708_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_708_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_708_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_708_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_177, KF_B_MODE_PROBS_709
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_709_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_709_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_709_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_709_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_177, KF_B_MODE_PROBS_710
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_710_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_710_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_710_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_710_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_177, KF_B_MODE_PROBS_711
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_711_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_711_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_711_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_177_KF_B_MODE_PROBS_711_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_OFFSET	(0x0AD4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_178, KF_B_MODE_PROBS_712
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_712_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_712_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_712_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_712_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_178, KF_B_MODE_PROBS_713
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_713_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_713_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_713_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_713_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_178, KF_B_MODE_PROBS_714
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_714_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_714_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_714_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_714_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_178, KF_B_MODE_PROBS_715
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_715_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_715_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_715_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_178_KF_B_MODE_PROBS_715_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_OFFSET	(0x0AD8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_179, KF_B_MODE_PROBS_716
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_716_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_716_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_716_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_716_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_179, KF_B_MODE_PROBS_717
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_717_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_717_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_717_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_717_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_179, KF_B_MODE_PROBS_718
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_718_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_718_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_718_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_718_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_179, KF_B_MODE_PROBS_719
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_719_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_719_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_719_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_179_KF_B_MODE_PROBS_719_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_OFFSET	(0x0ADC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_180, KF_B_MODE_PROBS_720
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_720_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_720_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_720_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_720_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_180, KF_B_MODE_PROBS_721
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_721_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_721_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_721_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_721_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_180, KF_B_MODE_PROBS_722
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_722_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_722_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_722_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_722_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_180, KF_B_MODE_PROBS_723
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_723_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_723_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_723_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_180_KF_B_MODE_PROBS_723_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_OFFSET	(0x0AE0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_181, KF_B_MODE_PROBS_724
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_724_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_724_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_724_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_724_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_181, KF_B_MODE_PROBS_725
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_725_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_725_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_725_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_725_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_181, KF_B_MODE_PROBS_726
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_726_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_726_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_726_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_726_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_181, KF_B_MODE_PROBS_727
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_727_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_727_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_727_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_181_KF_B_MODE_PROBS_727_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_OFFSET	(0x0AE4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_182, KF_B_MODE_PROBS_728
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_728_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_728_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_728_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_728_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_182, KF_B_MODE_PROBS_729
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_729_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_729_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_729_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_729_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_182, KF_B_MODE_PROBS_730
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_730_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_730_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_730_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_730_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_182, KF_B_MODE_PROBS_731
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_731_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_731_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_731_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_182_KF_B_MODE_PROBS_731_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_OFFSET	(0x0AE8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_183, KF_B_MODE_PROBS_732
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_732_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_732_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_732_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_732_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_183, KF_B_MODE_PROBS_733
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_733_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_733_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_733_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_733_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_183, KF_B_MODE_PROBS_734
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_734_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_734_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_734_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_734_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_183, KF_B_MODE_PROBS_735
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_735_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_735_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_735_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_183_KF_B_MODE_PROBS_735_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_OFFSET	(0x0AEC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_184, KF_B_MODE_PROBS_736
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_736_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_736_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_736_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_736_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_184, KF_B_MODE_PROBS_737
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_737_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_737_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_737_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_737_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_184, KF_B_MODE_PROBS_738
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_738_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_738_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_738_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_738_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_184, KF_B_MODE_PROBS_739
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_739_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_739_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_739_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_184_KF_B_MODE_PROBS_739_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_OFFSET	(0x0AF0)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_185, KF_B_MODE_PROBS_740
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_740_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_740_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_740_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_740_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_185, KF_B_MODE_PROBS_741
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_741_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_741_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_741_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_741_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_185, KF_B_MODE_PROBS_742
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_742_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_742_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_742_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_742_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_185, KF_B_MODE_PROBS_743
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_743_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_743_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_743_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_185_KF_B_MODE_PROBS_743_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_OFFSET	(0x0AF4)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_186, KF_B_MODE_PROBS_744
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_744_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_744_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_744_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_744_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_186, KF_B_MODE_PROBS_745
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_745_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_745_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_745_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_745_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_186, KF_B_MODE_PROBS_746
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_746_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_746_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_746_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_746_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_186, KF_B_MODE_PROBS_747
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_747_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_747_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_747_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_186_KF_B_MODE_PROBS_747_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_OFFSET	(0x0AF8)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_187, KF_B_MODE_PROBS_748
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_748_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_748_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_748_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_748_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_187, KF_B_MODE_PROBS_749
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_749_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_749_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_749_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_749_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_187, KF_B_MODE_PROBS_750
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_750_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_750_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_750_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_750_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_187, KF_B_MODE_PROBS_751
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_751_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_751_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_751_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_187_KF_B_MODE_PROBS_751_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_OFFSET	(0x0AFC)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_188, KF_B_MODE_PROBS_752
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_752_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_752_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_752_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_752_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_188, KF_B_MODE_PROBS_753
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_753_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_753_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_753_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_753_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_188, KF_B_MODE_PROBS_754
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_754_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_754_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_754_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_754_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_188, KF_B_MODE_PROBS_755
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_755_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_755_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_755_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_188_KF_B_MODE_PROBS_755_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_OFFSET	(0x0B00)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_189, KF_B_MODE_PROBS_756
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_756_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_756_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_756_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_756_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_189, KF_B_MODE_PROBS_757
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_757_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_757_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_757_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_757_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_189, KF_B_MODE_PROBS_758
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_758_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_758_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_758_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_758_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_189, KF_B_MODE_PROBS_759
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_759_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_759_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_759_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_189_KF_B_MODE_PROBS_759_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_OFFSET	(0x0B04)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_190, KF_B_MODE_PROBS_760
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_760_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_760_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_760_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_760_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_190, KF_B_MODE_PROBS_761
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_761_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_761_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_761_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_761_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_190, KF_B_MODE_PROBS_762
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_762_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_762_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_762_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_762_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_190, KF_B_MODE_PROBS_763
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_763_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_763_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_763_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_190_KF_B_MODE_PROBS_763_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_OFFSET	(0x0B08)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_191, KF_B_MODE_PROBS_764
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_764_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_764_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_764_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_764_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_191, KF_B_MODE_PROBS_765
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_765_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_765_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_765_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_765_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_191, KF_B_MODE_PROBS_766
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_766_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_766_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_766_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_766_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_191, KF_B_MODE_PROBS_767
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_767_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_767_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_767_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_191_KF_B_MODE_PROBS_767_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_OFFSET	(0x0B0C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_192, KF_B_MODE_PROBS_768
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_768_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_768_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_768_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_768_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_192, KF_B_MODE_PROBS_769
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_769_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_769_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_769_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_769_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_192, KF_B_MODE_PROBS_770
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_770_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_770_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_770_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_770_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_192, KF_B_MODE_PROBS_771
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_771_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_771_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_771_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_192_KF_B_MODE_PROBS_771_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_OFFSET	(0x0B10)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_193, KF_B_MODE_PROBS_772
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_772_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_772_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_772_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_772_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_193, KF_B_MODE_PROBS_773
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_773_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_773_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_773_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_773_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_193, KF_B_MODE_PROBS_774
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_774_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_774_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_774_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_774_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_193, KF_B_MODE_PROBS_775
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_775_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_775_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_775_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_193_KF_B_MODE_PROBS_775_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_OFFSET	(0x0B14)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_194, KF_B_MODE_PROBS_776
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_776_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_776_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_776_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_776_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_194, KF_B_MODE_PROBS_777
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_777_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_777_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_777_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_777_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_194, KF_B_MODE_PROBS_778
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_778_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_778_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_778_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_778_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_194, KF_B_MODE_PROBS_779
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_779_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_779_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_779_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_194_KF_B_MODE_PROBS_779_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_OFFSET	(0x0B18)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_195, KF_B_MODE_PROBS_780
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_780_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_780_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_780_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_780_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_195, KF_B_MODE_PROBS_781
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_781_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_781_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_781_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_781_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_195, KF_B_MODE_PROBS_782
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_782_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_782_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_782_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_782_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_195, KF_B_MODE_PROBS_783
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_783_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_783_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_783_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_195_KF_B_MODE_PROBS_783_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_OFFSET	(0x0B1C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_196, KF_B_MODE_PROBS_784
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_784_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_784_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_784_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_784_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_196, KF_B_MODE_PROBS_785
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_785_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_785_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_785_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_785_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_196, KF_B_MODE_PROBS_786
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_786_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_786_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_786_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_786_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_196, KF_B_MODE_PROBS_787
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_787_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_787_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_787_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_196_KF_B_MODE_PROBS_787_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_OFFSET	(0x0B20)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_197, KF_B_MODE_PROBS_788
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_788_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_788_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_788_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_788_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_197, KF_B_MODE_PROBS_789
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_789_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_789_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_789_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_789_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_197, KF_B_MODE_PROBS_790
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_790_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_790_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_790_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_790_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_197, KF_B_MODE_PROBS_791
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_791_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_791_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_791_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_197_KF_B_MODE_PROBS_791_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_OFFSET	(0x0B24)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_198, KF_B_MODE_PROBS_792
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_792_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_792_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_792_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_792_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_198, KF_B_MODE_PROBS_793
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_793_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_793_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_793_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_793_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_198, KF_B_MODE_PROBS_794
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_794_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_794_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_794_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_794_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_198, KF_B_MODE_PROBS_795
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_795_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_795_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_795_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_198_KF_B_MODE_PROBS_795_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_OFFSET	(0x0B28)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_199, KF_B_MODE_PROBS_796
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_796_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_796_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_796_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_796_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_199, KF_B_MODE_PROBS_797
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_797_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_797_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_797_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_797_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_199, KF_B_MODE_PROBS_798
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_798_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_798_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_798_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_798_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_199, KF_B_MODE_PROBS_799
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_799_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_799_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_799_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_199_KF_B_MODE_PROBS_799_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_OFFSET	(0x0B2C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_200, KF_B_MODE_PROBS_800
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_800_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_800_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_800_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_800_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_200, KF_B_MODE_PROBS_801
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_801_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_801_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_801_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_801_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_200, KF_B_MODE_PROBS_802
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_802_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_802_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_802_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_802_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_200, KF_B_MODE_PROBS_803
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_803_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_803_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_803_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_200_KF_B_MODE_PROBS_803_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_OFFSET	(0x0B30)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_201, KF_B_MODE_PROBS_804
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_804_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_804_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_804_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_804_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_201, KF_B_MODE_PROBS_805
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_805_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_805_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_805_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_805_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_201, KF_B_MODE_PROBS_806
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_806_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_806_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_806_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_806_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_201, KF_B_MODE_PROBS_807
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_807_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_807_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_807_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_201_KF_B_MODE_PROBS_807_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_OFFSET	(0x0B34)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_202, KF_B_MODE_PROBS_808
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_808_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_808_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_808_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_808_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_202, KF_B_MODE_PROBS_809
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_809_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_809_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_809_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_809_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_202, KF_B_MODE_PROBS_810
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_810_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_810_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_810_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_810_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_202, KF_B_MODE_PROBS_811
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_811_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_811_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_811_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_202_KF_B_MODE_PROBS_811_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_OFFSET	(0x0B38)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_203, KF_B_MODE_PROBS_812
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_812_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_812_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_812_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_812_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_203, KF_B_MODE_PROBS_813
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_813_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_813_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_813_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_813_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_203, KF_B_MODE_PROBS_814
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_814_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_814_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_814_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_814_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_203, KF_B_MODE_PROBS_815
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_815_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_815_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_815_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_203_KF_B_MODE_PROBS_815_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_OFFSET	(0x0B3C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_204, KF_B_MODE_PROBS_816
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_816_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_816_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_816_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_816_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_204, KF_B_MODE_PROBS_817
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_817_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_817_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_817_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_817_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_204, KF_B_MODE_PROBS_818
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_818_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_818_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_818_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_818_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_204, KF_B_MODE_PROBS_819
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_819_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_819_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_819_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_204_KF_B_MODE_PROBS_819_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_OFFSET	(0x0B40)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_205, KF_B_MODE_PROBS_820
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_820_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_820_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_820_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_820_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_205, KF_B_MODE_PROBS_821
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_821_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_821_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_821_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_821_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_205, KF_B_MODE_PROBS_822
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_822_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_822_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_822_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_822_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_205, KF_B_MODE_PROBS_823
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_823_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_823_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_823_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_205_KF_B_MODE_PROBS_823_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_OFFSET	(0x0B44)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_206, KF_B_MODE_PROBS_824
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_824_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_824_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_824_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_824_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_206, KF_B_MODE_PROBS_825
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_825_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_825_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_825_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_825_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_206, KF_B_MODE_PROBS_826
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_826_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_826_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_826_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_826_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_206, KF_B_MODE_PROBS_827
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_827_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_827_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_827_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_206_KF_B_MODE_PROBS_827_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_OFFSET	(0x0B48)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_207, KF_B_MODE_PROBS_828
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_828_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_828_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_828_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_828_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_207, KF_B_MODE_PROBS_829
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_829_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_829_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_829_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_829_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_207, KF_B_MODE_PROBS_830
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_830_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_830_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_830_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_830_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_207, KF_B_MODE_PROBS_831
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_831_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_831_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_831_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_207_KF_B_MODE_PROBS_831_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_OFFSET	(0x0B4C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_208, KF_B_MODE_PROBS_832
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_832_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_832_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_832_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_832_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_208, KF_B_MODE_PROBS_833
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_833_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_833_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_833_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_833_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_208, KF_B_MODE_PROBS_834
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_834_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_834_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_834_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_834_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_208, KF_B_MODE_PROBS_835
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_835_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_835_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_835_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_208_KF_B_MODE_PROBS_835_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_OFFSET	(0x0B50)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_209, KF_B_MODE_PROBS_836
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_836_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_836_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_836_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_836_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_209, KF_B_MODE_PROBS_837
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_837_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_837_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_837_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_837_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_209, KF_B_MODE_PROBS_838
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_838_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_838_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_838_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_838_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_209, KF_B_MODE_PROBS_839
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_839_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_839_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_839_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_209_KF_B_MODE_PROBS_839_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_OFFSET	(0x0B54)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_210, KF_B_MODE_PROBS_840
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_840_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_840_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_840_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_840_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_210, KF_B_MODE_PROBS_841
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_841_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_841_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_841_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_841_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_210, KF_B_MODE_PROBS_842
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_842_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_842_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_842_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_842_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_210, KF_B_MODE_PROBS_843
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_843_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_843_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_843_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_210_KF_B_MODE_PROBS_843_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_OFFSET	(0x0B58)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_211, KF_B_MODE_PROBS_844
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_844_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_844_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_844_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_844_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_211, KF_B_MODE_PROBS_845
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_845_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_845_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_845_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_845_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_211, KF_B_MODE_PROBS_846
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_846_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_846_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_846_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_846_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_211, KF_B_MODE_PROBS_847
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_847_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_847_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_847_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_211_KF_B_MODE_PROBS_847_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_OFFSET	(0x0B5C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_212, KF_B_MODE_PROBS_848
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_848_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_848_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_848_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_848_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_212, KF_B_MODE_PROBS_849
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_849_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_849_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_849_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_849_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_212, KF_B_MODE_PROBS_850
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_850_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_850_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_850_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_850_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_212, KF_B_MODE_PROBS_851
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_851_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_851_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_851_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_212_KF_B_MODE_PROBS_851_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_OFFSET	(0x0B60)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_213, KF_B_MODE_PROBS_852
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_852_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_852_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_852_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_852_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_213, KF_B_MODE_PROBS_853
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_853_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_853_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_853_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_853_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_213, KF_B_MODE_PROBS_854
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_854_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_854_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_854_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_854_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_213, KF_B_MODE_PROBS_855
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_855_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_855_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_855_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_213_KF_B_MODE_PROBS_855_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_OFFSET	(0x0B64)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_214, KF_B_MODE_PROBS_856
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_856_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_856_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_856_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_856_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_214, KF_B_MODE_PROBS_857
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_857_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_857_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_857_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_857_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_214, KF_B_MODE_PROBS_858
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_858_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_858_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_858_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_858_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_214, KF_B_MODE_PROBS_859
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_859_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_859_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_859_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_214_KF_B_MODE_PROBS_859_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_OFFSET	(0x0B68)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_215, KF_B_MODE_PROBS_860
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_860_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_860_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_860_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_860_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_215, KF_B_MODE_PROBS_861
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_861_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_861_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_861_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_861_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_215, KF_B_MODE_PROBS_862
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_862_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_862_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_862_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_862_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_215, KF_B_MODE_PROBS_863
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_863_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_863_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_863_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_215_KF_B_MODE_PROBS_863_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_OFFSET	(0x0B6C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_216, KF_B_MODE_PROBS_864
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_864_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_864_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_864_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_864_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_216, KF_B_MODE_PROBS_865
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_865_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_865_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_865_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_865_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_216, KF_B_MODE_PROBS_866
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_866_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_866_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_866_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_866_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_216, KF_B_MODE_PROBS_867
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_867_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_867_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_867_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_216_KF_B_MODE_PROBS_867_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_OFFSET	(0x0B70)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_217, KF_B_MODE_PROBS_868
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_868_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_868_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_868_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_868_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_217, KF_B_MODE_PROBS_869
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_869_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_869_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_869_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_869_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_217, KF_B_MODE_PROBS_870
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_870_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_870_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_870_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_870_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_217, KF_B_MODE_PROBS_871
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_871_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_871_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_871_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_217_KF_B_MODE_PROBS_871_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_OFFSET	(0x0B74)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_218, KF_B_MODE_PROBS_872
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_872_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_872_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_872_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_872_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_218, KF_B_MODE_PROBS_873
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_873_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_873_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_873_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_873_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_218, KF_B_MODE_PROBS_874
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_874_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_874_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_874_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_874_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_218, KF_B_MODE_PROBS_875
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_875_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_875_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_875_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_218_KF_B_MODE_PROBS_875_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_OFFSET	(0x0B78)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_219, KF_B_MODE_PROBS_876
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_876_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_876_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_876_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_876_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_219, KF_B_MODE_PROBS_877
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_877_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_877_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_877_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_877_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_219, KF_B_MODE_PROBS_878
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_878_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_878_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_878_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_878_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_219, KF_B_MODE_PROBS_879
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_879_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_879_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_879_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_219_KF_B_MODE_PROBS_879_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_OFFSET	(0x0B7C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_220, KF_B_MODE_PROBS_880
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_880_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_880_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_880_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_880_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_220, KF_B_MODE_PROBS_881
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_881_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_881_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_881_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_881_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_220, KF_B_MODE_PROBS_882
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_882_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_882_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_882_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_882_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_220, KF_B_MODE_PROBS_883
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_883_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_883_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_883_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_220_KF_B_MODE_PROBS_883_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_OFFSET	(0x0B80)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_221, KF_B_MODE_PROBS_884
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_884_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_884_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_884_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_884_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_221, KF_B_MODE_PROBS_885
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_885_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_885_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_885_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_885_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_221, KF_B_MODE_PROBS_886
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_886_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_886_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_886_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_886_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_221, KF_B_MODE_PROBS_887
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_887_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_887_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_887_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_221_KF_B_MODE_PROBS_887_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_OFFSET	(0x0B84)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_222, KF_B_MODE_PROBS_888
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_888_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_888_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_888_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_888_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_222, KF_B_MODE_PROBS_889
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_889_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_889_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_889_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_889_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_222, KF_B_MODE_PROBS_890
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_890_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_890_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_890_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_890_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_222, KF_B_MODE_PROBS_891
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_891_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_891_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_891_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_222_KF_B_MODE_PROBS_891_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_OFFSET	(0x0B88)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_223, KF_B_MODE_PROBS_892
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_892_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_892_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_892_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_892_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_223, KF_B_MODE_PROBS_893
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_893_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_893_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_893_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_893_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_223, KF_B_MODE_PROBS_894
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_894_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_894_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_894_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_894_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_223, KF_B_MODE_PROBS_895
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_895_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_895_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_895_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_223_KF_B_MODE_PROBS_895_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_OFFSET	(0x0B8C)

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_224, KF_B_MODE_PROBS_896
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_896_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_896_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_896_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_896_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_224, KF_B_MODE_PROBS_897
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_897_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_897_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_897_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_897_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_224, KF_B_MODE_PROBS_898
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_898_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_898_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_898_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_898_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, KF_B_MODE_PROBS_REG_224, KF_B_MODE_PROBS_899
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_899_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_899_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_899_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_KF_B_MODE_PROBS_REG_224_KF_B_MODE_PROBS_899_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_OFFSET	(0x0B90)

// MSVDX_VEC_LINE_STORE_RAM, MB_NKF_PROBS_REG_00, INTRA_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_INTRA_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_INTRA_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_INTRA_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_INTRA_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MB_NKF_PROBS_REG_00, LAST_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_LAST_PROBS_00_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_LAST_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_LAST_PROBS_00_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_LAST_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MB_NKF_PROBS_REG_00, GF_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_GF_PROBS_00_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_GF_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_GF_PROBS_00_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MB_NKF_PROBS_REG_00_GF_PROBS_00_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_OFFSET	(0x0B94)

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_00, NKF_B_MODE_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_00, NKF_B_MODE_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_00, NKF_B_MODE_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_00, NKF_B_MODE_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_03_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_00_NKF_B_MODE_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_OFFSET	(0x0B98)

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_01, NKF_B_MODE_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_04_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_01, NKF_B_MODE_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_05_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_05_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_01, NKF_B_MODE_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_06_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_06_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_01, NKF_B_MODE_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_07_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_07_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_01_NKF_B_MODE_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_02_OFFSET	(0x0B9C)

// MSVDX_VEC_LINE_STORE_RAM, NKF_B_MODE_PROBS_REG_02, NKF_B_MODE_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_02_NKF_B_MODE_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_02_NKF_B_MODE_PROBS_08_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_02_NKF_B_MODE_PROBS_08_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_NKF_B_MODE_PROBS_REG_02_NKF_B_MODE_PROBS_08_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_OFFSET	(0x0BA0)

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_00, MODE_CONTEXT_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_00, MODE_CONTEXT_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_00, MODE_CONTEXT_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_00, MODE_CONTEXT_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_03_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_00_MODE_CONTEXT_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_OFFSET	(0x0BA4)

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_01, MODE_CONTEXT_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_04_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_01, MODE_CONTEXT_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_05_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_05_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_01, MODE_CONTEXT_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_06_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_06_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_01, MODE_CONTEXT_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_07_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_07_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_01_MODE_CONTEXT_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_OFFSET	(0x0BA8)

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_02, MODE_CONTEXT_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_08_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_08_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_02, MODE_CONTEXT_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_09_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_09_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_02, MODE_CONTEXT_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_10_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_10_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_10_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_02, MODE_CONTEXT_PROBS_11
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_11_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_11_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_11_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_02_MODE_CONTEXT_PROBS_11_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_OFFSET	(0x0BAC)

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_03, MODE_CONTEXT_PROBS_12
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_12_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_12_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_12_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_12_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_03, MODE_CONTEXT_PROBS_13
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_13_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_13_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_13_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_13_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_03, MODE_CONTEXT_PROBS_14
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_14_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_14_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_14_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_14_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_03, MODE_CONTEXT_PROBS_15
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_15_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_15_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_15_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_03_MODE_CONTEXT_PROBS_15_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_OFFSET	(0x0BB0)

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_04, MODE_CONTEXT_PROBS_16
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_16_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_16_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_16_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_16_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_04, MODE_CONTEXT_PROBS_17
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_17_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_17_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_17_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_17_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_04, MODE_CONTEXT_PROBS_18
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_18_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_18_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_18_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_18_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_04, MODE_CONTEXT_PROBS_19
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_19_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_19_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_19_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_04_MODE_CONTEXT_PROBS_19_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_OFFSET	(0x0BB4)

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_05, MODE_CONTEXT_PROBS_20
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_20_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_20_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_20_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_20_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_05, MODE_CONTEXT_PROBS_21
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_21_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_21_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_21_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_21_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_05, MODE_CONTEXT_PROBS_22
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_22_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_22_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_22_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_22_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MODE_CONTEXT_PROBS_REG_05, MODE_CONTEXT_PROBS_23
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_23_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_23_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_23_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MODE_CONTEXT_PROBS_REG_05_MODE_CONTEXT_PROBS_23_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_OFFSET	(0x0BB8)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_00, MV_CONTEXT_X_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_00, MV_CONTEXT_X_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_00, MV_CONTEXT_X_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_00, MV_CONTEXT_X_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_03_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_00_MV_CONTEXT_X_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_OFFSET	(0x0BBC)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_01, MV_CONTEXT_X_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_04_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_01, MV_CONTEXT_X_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_05_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_05_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_01, MV_CONTEXT_X_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_06_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_06_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_01, MV_CONTEXT_X_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_07_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_07_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_01_MV_CONTEXT_X_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_OFFSET	(0x0BC0)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_02, MV_CONTEXT_X_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_08_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_08_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_02, MV_CONTEXT_X_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_09_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_09_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_02, MV_CONTEXT_X_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_10_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_10_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_10_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_02, MV_CONTEXT_X_PROBS_11
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_11_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_11_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_11_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_02_MV_CONTEXT_X_PROBS_11_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_OFFSET	(0x0BC4)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_03, MV_CONTEXT_X_PROBS_12
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_12_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_12_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_12_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_12_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_03, MV_CONTEXT_X_PROBS_13
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_13_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_13_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_13_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_13_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_03, MV_CONTEXT_X_PROBS_14
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_14_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_14_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_14_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_14_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_03, MV_CONTEXT_X_PROBS_15
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_15_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_15_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_15_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_03_MV_CONTEXT_X_PROBS_15_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_OFFSET	(0x0BC8)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_04, MV_CONTEXT_X_PROBS_16
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_16_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_16_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_16_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_16_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_04, MV_CONTEXT_X_PROBS_17
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_17_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_17_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_17_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_17_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_X_PROBS_REG_04, MV_CONTEXT_X_PROBS_18
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_18_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_18_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_18_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_X_PROBS_REG_04_MV_CONTEXT_X_PROBS_18_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_OFFSET	(0x0BCC)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_00, MV_CONTEXT_Y_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_00, MV_CONTEXT_Y_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_00, MV_CONTEXT_Y_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_00, MV_CONTEXT_Y_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_03_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_00_MV_CONTEXT_Y_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_OFFSET	(0x0BD0)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_01, MV_CONTEXT_Y_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_04_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_01, MV_CONTEXT_Y_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_05_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_05_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_01, MV_CONTEXT_Y_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_06_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_06_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_01, MV_CONTEXT_Y_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_07_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_07_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_01_MV_CONTEXT_Y_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_OFFSET	(0x0BD4)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_02, MV_CONTEXT_Y_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_08_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_08_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_02, MV_CONTEXT_Y_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_09_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_09_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_02, MV_CONTEXT_Y_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_10_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_10_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_10_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_02, MV_CONTEXT_Y_PROBS_11
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_11_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_11_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_11_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_02_MV_CONTEXT_Y_PROBS_11_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_OFFSET	(0x0BD8)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_03, MV_CONTEXT_Y_PROBS_12
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_12_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_12_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_12_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_12_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_03, MV_CONTEXT_Y_PROBS_13
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_13_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_13_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_13_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_13_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_03, MV_CONTEXT_Y_PROBS_14
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_14_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_14_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_14_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_14_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_03, MV_CONTEXT_Y_PROBS_15
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_15_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_15_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_15_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_03_MV_CONTEXT_Y_PROBS_15_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_OFFSET	(0x0BDC)

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_04, MV_CONTEXT_Y_PROBS_16
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_16_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_16_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_16_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_16_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_04, MV_CONTEXT_Y_PROBS_17
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_17_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_17_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_17_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_17_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_CONTEXT_Y_PROBS_REG_04, MV_CONTEXT_Y_PROBS_18
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_18_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_18_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_18_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_CONTEXT_Y_PROBS_REG_04_MV_CONTEXT_Y_PROBS_18_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_OFFSET	(0x0BE0)

// MSVDX_VEC_LINE_STORE_RAM, MV_PARTITION_PROBS_REG_00, MV_PARTITION_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_PARTITION_PROBS_REG_00, MV_PARTITION_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, MV_PARTITION_PROBS_REG_00, MV_PARTITION_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_MV_PARTITION_PROBS_REG_00_MV_PARTITION_PROBS_02_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_OFFSET	(0x0BE4)

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_00, SUB_MV_REF_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_00, SUB_MV_REF_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_00, SUB_MV_REF_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_00, SUB_MV_REF_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_03_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_00_SUB_MV_REF_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_OFFSET	(0x0BE8)

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_01, SUB_MV_REF_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_04_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_01, SUB_MV_REF_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_05_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_05_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_01, SUB_MV_REF_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_06_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_06_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_01, SUB_MV_REF_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_07_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_07_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_01_SUB_MV_REF_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_OFFSET	(0x0BEC)

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_02, SUB_MV_REF_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_08_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_08_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_02, SUB_MV_REF_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_09_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_09_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_02, SUB_MV_REF_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_10_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_10_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_10_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_02, SUB_MV_REF_PROBS_11
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_11_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_11_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_11_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_02_SUB_MV_REF_PROBS_11_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_OFFSET	(0x0BF0)

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_03, SUB_MV_REF_PROBS_12
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_12_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_12_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_12_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_12_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_03, SUB_MV_REF_PROBS_13
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_13_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_13_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_13_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_13_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, SUB_MV_REF_PROBS_REG_03, SUB_MV_REF_PROBS_14
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_14_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_14_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_14_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_SUB_MV_REF_PROBS_REG_03_SUB_MV_REF_PROBS_14_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_OFFSET	(0x0BF4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_00, COEFF_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_00_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_00_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_00, COEFF_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_01_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_01_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_00, COEFF_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_02_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_02_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_00, COEFF_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_03_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_03_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_00_COEFF_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_OFFSET	(0x0BF8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_01, COEFF_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_04_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_04_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_01, COEFF_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_05_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_05_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_01, COEFF_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_06_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_06_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_01, COEFF_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_07_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_07_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_01_COEFF_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_OFFSET	(0x0BFC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_02, COEFF_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_08_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_08_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_02, COEFF_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_09_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_09_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_02, COEFF_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_10_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_10_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_10_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_02, COEFF_PROBS_11
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_11_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_11_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_11_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_02_COEFF_PROBS_11_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_OFFSET	(0x0C00)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_03, COEFF_PROBS_12
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_12_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_12_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_12_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_12_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_03, COEFF_PROBS_13
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_13_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_13_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_13_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_13_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_03, COEFF_PROBS_14
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_14_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_14_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_14_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_14_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_03, COEFF_PROBS_15
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_15_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_15_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_15_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_03_COEFF_PROBS_15_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_OFFSET	(0x0C04)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_04, COEFF_PROBS_16
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_16_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_16_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_16_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_16_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_04, COEFF_PROBS_17
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_17_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_17_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_17_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_17_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_04, COEFF_PROBS_18
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_18_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_18_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_18_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_18_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_04, COEFF_PROBS_19
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_19_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_19_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_19_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_04_COEFF_PROBS_19_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_OFFSET	(0x0C08)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_05, COEFF_PROBS_20
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_20_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_20_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_20_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_20_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_05, COEFF_PROBS_21
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_21_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_21_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_21_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_21_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_05, COEFF_PROBS_22
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_22_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_22_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_22_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_22_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_05, COEFF_PROBS_23
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_23_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_23_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_23_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_05_COEFF_PROBS_23_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_OFFSET	(0x0C0C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_06, COEFF_PROBS_24
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_24_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_24_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_24_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_24_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_06, COEFF_PROBS_25
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_25_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_25_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_25_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_25_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_06, COEFF_PROBS_26
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_26_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_26_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_26_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_26_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_06, COEFF_PROBS_27
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_27_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_27_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_27_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_06_COEFF_PROBS_27_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_OFFSET	(0x0C10)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_07, COEFF_PROBS_28
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_28_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_28_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_28_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_28_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_07, COEFF_PROBS_29
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_29_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_29_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_29_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_29_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_07, COEFF_PROBS_30
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_30_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_30_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_30_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_30_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_07, COEFF_PROBS_31
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_31_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_31_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_31_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_07_COEFF_PROBS_31_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_OFFSET	(0x0C14)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_08, COEFF_PROBS_32
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_32_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_32_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_32_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_32_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_08, COEFF_PROBS_33
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_33_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_33_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_33_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_33_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_08, COEFF_PROBS_34
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_34_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_34_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_34_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_34_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_08, COEFF_PROBS_35
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_35_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_35_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_35_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_08_COEFF_PROBS_35_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_OFFSET	(0x0C18)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_09, COEFF_PROBS_36
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_36_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_36_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_36_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_36_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_09, COEFF_PROBS_37
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_37_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_37_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_37_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_37_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_09, COEFF_PROBS_38
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_38_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_38_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_38_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_38_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_09, COEFF_PROBS_39
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_39_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_39_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_39_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_09_COEFF_PROBS_39_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_OFFSET	(0x0C1C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_10, COEFF_PROBS_40
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_40_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_40_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_40_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_40_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_10, COEFF_PROBS_41
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_41_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_41_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_41_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_41_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_10, COEFF_PROBS_42
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_42_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_42_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_42_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_42_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_10, COEFF_PROBS_43
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_43_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_43_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_43_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_10_COEFF_PROBS_43_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_OFFSET	(0x0C20)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_11, COEFF_PROBS_44
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_44_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_44_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_44_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_44_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_11, COEFF_PROBS_45
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_45_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_45_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_45_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_45_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_11, COEFF_PROBS_46
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_46_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_46_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_46_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_46_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_11, COEFF_PROBS_47
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_47_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_47_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_47_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_11_COEFF_PROBS_47_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_OFFSET	(0x0C24)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_12, COEFF_PROBS_48
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_48_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_48_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_48_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_48_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_12, COEFF_PROBS_49
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_49_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_49_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_49_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_49_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_12, COEFF_PROBS_50
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_50_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_50_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_50_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_50_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_12, COEFF_PROBS_51
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_51_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_51_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_51_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_12_COEFF_PROBS_51_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_OFFSET	(0x0C28)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_13, COEFF_PROBS_52
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_52_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_52_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_52_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_52_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_13, COEFF_PROBS_53
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_53_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_53_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_53_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_53_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_13, COEFF_PROBS_54
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_54_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_54_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_54_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_54_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_13, COEFF_PROBS_55
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_55_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_55_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_55_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_13_COEFF_PROBS_55_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_OFFSET	(0x0C2C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_14, COEFF_PROBS_56
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_56_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_56_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_56_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_56_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_14, COEFF_PROBS_57
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_57_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_57_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_57_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_57_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_14, COEFF_PROBS_58
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_58_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_58_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_58_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_58_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_14, COEFF_PROBS_59
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_59_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_59_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_59_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_14_COEFF_PROBS_59_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_OFFSET	(0x0C30)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_15, COEFF_PROBS_60
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_60_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_60_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_60_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_60_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_15, COEFF_PROBS_61
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_61_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_61_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_61_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_61_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_15, COEFF_PROBS_62
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_62_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_62_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_62_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_62_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_15, COEFF_PROBS_63
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_63_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_63_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_63_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_15_COEFF_PROBS_63_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_OFFSET	(0x0C34)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_16, COEFF_PROBS_64
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_64_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_64_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_64_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_64_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_16, COEFF_PROBS_65
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_65_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_65_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_65_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_65_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_16, COEFF_PROBS_66
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_66_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_66_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_66_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_66_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_16, COEFF_PROBS_67
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_67_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_67_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_67_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_16_COEFF_PROBS_67_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_OFFSET	(0x0C38)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_17, COEFF_PROBS_68
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_68_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_68_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_68_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_68_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_17, COEFF_PROBS_69
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_69_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_69_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_69_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_69_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_17, COEFF_PROBS_70
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_70_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_70_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_70_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_70_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_17, COEFF_PROBS_71
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_71_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_71_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_71_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_17_COEFF_PROBS_71_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_OFFSET	(0x0C3C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_18, COEFF_PROBS_72
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_72_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_72_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_72_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_72_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_18, COEFF_PROBS_73
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_73_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_73_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_73_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_73_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_18, COEFF_PROBS_74
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_74_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_74_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_74_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_74_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_18, COEFF_PROBS_75
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_75_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_75_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_75_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_18_COEFF_PROBS_75_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_OFFSET	(0x0C40)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_19, COEFF_PROBS_76
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_76_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_76_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_76_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_76_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_19, COEFF_PROBS_77
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_77_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_77_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_77_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_77_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_19, COEFF_PROBS_78
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_78_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_78_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_78_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_78_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_19, COEFF_PROBS_79
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_79_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_79_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_79_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_19_COEFF_PROBS_79_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_OFFSET	(0x0C44)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_20, COEFF_PROBS_80
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_80_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_80_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_80_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_80_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_20, COEFF_PROBS_81
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_81_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_81_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_81_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_81_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_20, COEFF_PROBS_82
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_82_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_82_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_82_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_82_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_20, COEFF_PROBS_83
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_83_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_83_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_83_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_20_COEFF_PROBS_83_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_OFFSET	(0x0C48)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_21, COEFF_PROBS_84
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_84_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_84_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_84_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_84_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_21, COEFF_PROBS_85
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_85_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_85_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_85_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_85_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_21, COEFF_PROBS_86
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_86_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_86_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_86_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_86_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_21, COEFF_PROBS_87
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_87_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_87_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_87_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_21_COEFF_PROBS_87_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_OFFSET	(0x0C4C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_22, COEFF_PROBS_88
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_88_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_88_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_88_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_88_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_22, COEFF_PROBS_89
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_89_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_89_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_89_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_89_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_22, COEFF_PROBS_90
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_90_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_90_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_90_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_90_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_22, COEFF_PROBS_91
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_91_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_91_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_91_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_22_COEFF_PROBS_91_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_OFFSET	(0x0C50)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_23, COEFF_PROBS_92
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_92_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_92_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_92_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_92_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_23, COEFF_PROBS_93
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_93_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_93_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_93_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_93_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_23, COEFF_PROBS_94
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_94_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_94_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_94_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_94_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_23, COEFF_PROBS_95
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_95_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_95_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_95_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_23_COEFF_PROBS_95_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_OFFSET	(0x0C54)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_24, COEFF_PROBS_96
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_96_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_96_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_96_SHIFT	(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_96_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_24, COEFF_PROBS_97
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_97_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_97_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_97_SHIFT	(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_97_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_24, COEFF_PROBS_98
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_98_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_98_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_98_SHIFT	(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_98_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_24, COEFF_PROBS_99
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_99_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_99_LSBMASK	(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_99_SHIFT	(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_24_COEFF_PROBS_99_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_OFFSET	(0x0C58)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_25, COEFF_PROBS_100
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_100_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_100_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_100_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_100_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_25, COEFF_PROBS_101
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_101_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_101_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_101_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_101_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_25, COEFF_PROBS_102
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_102_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_102_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_102_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_102_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_25, COEFF_PROBS_103
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_103_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_103_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_103_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_25_COEFF_PROBS_103_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_OFFSET	(0x0C5C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_26, COEFF_PROBS_104
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_104_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_104_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_104_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_104_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_26, COEFF_PROBS_105
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_105_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_105_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_105_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_105_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_26, COEFF_PROBS_106
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_106_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_106_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_106_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_106_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_26, COEFF_PROBS_107
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_107_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_107_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_107_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_26_COEFF_PROBS_107_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_OFFSET	(0x0C60)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_27, COEFF_PROBS_108
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_108_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_108_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_108_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_108_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_27, COEFF_PROBS_109
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_109_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_109_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_109_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_109_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_27, COEFF_PROBS_110
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_110_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_110_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_110_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_110_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_27, COEFF_PROBS_111
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_111_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_111_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_111_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_27_COEFF_PROBS_111_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_OFFSET	(0x0C64)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_28, COEFF_PROBS_112
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_112_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_112_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_112_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_112_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_28, COEFF_PROBS_113
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_113_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_113_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_113_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_113_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_28, COEFF_PROBS_114
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_114_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_114_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_114_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_114_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_28, COEFF_PROBS_115
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_115_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_115_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_115_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_28_COEFF_PROBS_115_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_OFFSET	(0x0C68)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_29, COEFF_PROBS_116
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_116_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_116_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_116_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_116_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_29, COEFF_PROBS_117
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_117_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_117_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_117_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_117_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_29, COEFF_PROBS_118
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_118_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_118_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_118_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_118_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_29, COEFF_PROBS_119
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_119_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_119_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_119_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_29_COEFF_PROBS_119_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_OFFSET	(0x0C6C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_30, COEFF_PROBS_120
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_120_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_120_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_120_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_120_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_30, COEFF_PROBS_121
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_121_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_121_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_121_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_121_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_30, COEFF_PROBS_122
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_122_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_122_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_122_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_122_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_30, COEFF_PROBS_123
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_123_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_123_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_123_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_30_COEFF_PROBS_123_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_OFFSET	(0x0C70)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_31, COEFF_PROBS_124
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_124_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_124_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_124_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_124_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_31, COEFF_PROBS_125
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_125_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_125_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_125_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_125_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_31, COEFF_PROBS_126
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_126_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_126_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_126_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_126_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_31, COEFF_PROBS_127
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_127_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_127_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_127_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_31_COEFF_PROBS_127_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_OFFSET	(0x0C74)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_32, COEFF_PROBS_128
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_128_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_128_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_128_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_128_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_32, COEFF_PROBS_129
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_129_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_129_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_129_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_129_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_32, COEFF_PROBS_130
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_130_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_130_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_130_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_130_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_32, COEFF_PROBS_131
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_131_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_131_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_131_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_32_COEFF_PROBS_131_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_OFFSET	(0x0C78)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_33, COEFF_PROBS_132
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_132_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_132_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_132_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_132_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_33, COEFF_PROBS_133
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_133_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_133_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_133_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_133_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_33, COEFF_PROBS_134
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_134_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_134_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_134_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_134_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_33, COEFF_PROBS_135
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_135_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_135_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_135_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_33_COEFF_PROBS_135_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_OFFSET	(0x0C7C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_34, COEFF_PROBS_136
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_136_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_136_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_136_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_136_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_34, COEFF_PROBS_137
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_137_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_137_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_137_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_137_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_34, COEFF_PROBS_138
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_138_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_138_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_138_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_138_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_34, COEFF_PROBS_139
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_139_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_139_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_139_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_34_COEFF_PROBS_139_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_OFFSET	(0x0C80)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_35, COEFF_PROBS_140
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_140_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_140_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_140_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_140_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_35, COEFF_PROBS_141
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_141_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_141_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_141_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_141_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_35, COEFF_PROBS_142
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_142_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_142_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_142_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_142_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_35, COEFF_PROBS_143
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_143_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_143_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_143_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_35_COEFF_PROBS_143_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_OFFSET	(0x0C84)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_36, COEFF_PROBS_144
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_144_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_144_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_144_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_144_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_36, COEFF_PROBS_145
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_145_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_145_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_145_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_145_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_36, COEFF_PROBS_146
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_146_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_146_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_146_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_146_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_36, COEFF_PROBS_147
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_147_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_147_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_147_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_36_COEFF_PROBS_147_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_OFFSET	(0x0C88)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_37, COEFF_PROBS_148
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_148_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_148_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_148_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_148_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_37, COEFF_PROBS_149
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_149_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_149_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_149_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_149_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_37, COEFF_PROBS_150
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_150_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_150_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_150_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_150_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_37, COEFF_PROBS_151
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_151_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_151_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_151_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_37_COEFF_PROBS_151_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_OFFSET	(0x0C8C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_38, COEFF_PROBS_152
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_152_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_152_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_152_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_152_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_38, COEFF_PROBS_153
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_153_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_153_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_153_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_153_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_38, COEFF_PROBS_154
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_154_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_154_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_154_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_154_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_38, COEFF_PROBS_155
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_155_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_155_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_155_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_38_COEFF_PROBS_155_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_OFFSET	(0x0C90)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_39, COEFF_PROBS_156
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_156_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_156_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_156_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_156_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_39, COEFF_PROBS_157
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_157_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_157_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_157_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_157_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_39, COEFF_PROBS_158
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_158_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_158_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_158_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_158_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_39, COEFF_PROBS_159
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_159_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_159_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_159_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_39_COEFF_PROBS_159_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_OFFSET	(0x0C94)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_40, COEFF_PROBS_160
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_160_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_160_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_160_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_160_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_40, COEFF_PROBS_161
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_161_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_161_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_161_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_161_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_40, COEFF_PROBS_162
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_162_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_162_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_162_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_162_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_40, COEFF_PROBS_163
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_163_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_163_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_163_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_40_COEFF_PROBS_163_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_OFFSET	(0x0C98)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_41, COEFF_PROBS_164
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_164_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_164_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_164_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_164_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_41, COEFF_PROBS_165
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_165_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_165_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_165_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_165_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_41, COEFF_PROBS_166
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_166_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_166_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_166_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_166_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_41, COEFF_PROBS_167
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_167_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_167_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_167_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_41_COEFF_PROBS_167_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_OFFSET	(0x0C9C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_42, COEFF_PROBS_168
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_168_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_168_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_168_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_168_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_42, COEFF_PROBS_169
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_169_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_169_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_169_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_169_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_42, COEFF_PROBS_170
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_170_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_170_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_170_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_170_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_42, COEFF_PROBS_171
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_171_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_171_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_171_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_42_COEFF_PROBS_171_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_OFFSET	(0x0CA0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_43, COEFF_PROBS_172
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_172_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_172_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_172_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_172_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_43, COEFF_PROBS_173
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_173_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_173_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_173_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_173_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_43, COEFF_PROBS_174
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_174_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_174_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_174_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_174_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_43, COEFF_PROBS_175
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_175_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_175_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_175_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_43_COEFF_PROBS_175_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_OFFSET	(0x0CA4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_44, COEFF_PROBS_176
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_176_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_176_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_176_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_176_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_44, COEFF_PROBS_177
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_177_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_177_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_177_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_177_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_44, COEFF_PROBS_178
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_178_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_178_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_178_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_178_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_44, COEFF_PROBS_179
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_179_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_179_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_179_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_44_COEFF_PROBS_179_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_OFFSET	(0x0CA8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_45, COEFF_PROBS_180
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_180_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_180_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_180_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_180_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_45, COEFF_PROBS_181
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_181_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_181_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_181_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_181_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_45, COEFF_PROBS_182
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_182_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_182_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_182_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_182_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_45, COEFF_PROBS_183
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_183_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_183_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_183_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_45_COEFF_PROBS_183_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_OFFSET	(0x0CAC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_46, COEFF_PROBS_184
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_184_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_184_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_184_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_184_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_46, COEFF_PROBS_185
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_185_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_185_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_185_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_185_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_46, COEFF_PROBS_186
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_186_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_186_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_186_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_186_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_46, COEFF_PROBS_187
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_187_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_187_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_187_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_46_COEFF_PROBS_187_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_OFFSET	(0x0CB0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_47, COEFF_PROBS_188
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_188_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_188_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_188_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_188_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_47, COEFF_PROBS_189
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_189_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_189_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_189_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_189_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_47, COEFF_PROBS_190
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_190_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_190_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_190_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_190_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_47, COEFF_PROBS_191
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_191_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_191_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_191_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_47_COEFF_PROBS_191_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_OFFSET	(0x0CB4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_48, COEFF_PROBS_192
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_192_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_192_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_192_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_192_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_48, COEFF_PROBS_193
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_193_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_193_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_193_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_193_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_48, COEFF_PROBS_194
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_194_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_194_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_194_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_194_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_48, COEFF_PROBS_195
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_195_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_195_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_195_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_48_COEFF_PROBS_195_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_OFFSET	(0x0CB8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_49, COEFF_PROBS_196
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_196_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_196_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_196_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_196_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_49, COEFF_PROBS_197
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_197_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_197_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_197_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_197_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_49, COEFF_PROBS_198
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_198_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_198_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_198_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_198_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_49, COEFF_PROBS_199
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_199_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_199_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_199_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_49_COEFF_PROBS_199_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_OFFSET	(0x0CBC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_50, COEFF_PROBS_200
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_200_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_200_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_200_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_200_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_50, COEFF_PROBS_201
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_201_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_201_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_201_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_201_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_50, COEFF_PROBS_202
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_202_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_202_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_202_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_202_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_50, COEFF_PROBS_203
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_203_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_203_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_203_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_50_COEFF_PROBS_203_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_OFFSET	(0x0CC0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_51, COEFF_PROBS_204
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_204_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_204_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_204_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_204_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_51, COEFF_PROBS_205
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_205_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_205_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_205_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_205_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_51, COEFF_PROBS_206
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_206_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_206_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_206_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_206_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_51, COEFF_PROBS_207
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_207_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_207_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_207_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_51_COEFF_PROBS_207_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_OFFSET	(0x0CC4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_52, COEFF_PROBS_208
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_208_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_208_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_208_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_208_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_52, COEFF_PROBS_209
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_209_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_209_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_209_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_209_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_52, COEFF_PROBS_210
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_210_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_210_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_210_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_210_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_52, COEFF_PROBS_211
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_211_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_211_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_211_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_52_COEFF_PROBS_211_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_OFFSET	(0x0CC8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_53, COEFF_PROBS_212
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_212_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_212_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_212_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_212_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_53, COEFF_PROBS_213
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_213_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_213_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_213_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_213_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_53, COEFF_PROBS_214
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_214_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_214_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_214_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_214_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_53, COEFF_PROBS_215
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_215_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_215_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_215_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_53_COEFF_PROBS_215_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_OFFSET	(0x0CCC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_54, COEFF_PROBS_216
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_216_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_216_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_216_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_216_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_54, COEFF_PROBS_217
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_217_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_217_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_217_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_217_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_54, COEFF_PROBS_218
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_218_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_218_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_218_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_218_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_54, COEFF_PROBS_219
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_219_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_219_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_219_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_54_COEFF_PROBS_219_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_OFFSET	(0x0CD0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_55, COEFF_PROBS_220
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_220_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_220_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_220_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_220_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_55, COEFF_PROBS_221
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_221_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_221_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_221_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_221_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_55, COEFF_PROBS_222
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_222_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_222_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_222_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_222_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_55, COEFF_PROBS_223
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_223_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_223_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_223_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_55_COEFF_PROBS_223_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_OFFSET	(0x0CD4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_56, COEFF_PROBS_224
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_224_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_224_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_224_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_224_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_56, COEFF_PROBS_225
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_225_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_225_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_225_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_225_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_56, COEFF_PROBS_226
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_226_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_226_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_226_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_226_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_56, COEFF_PROBS_227
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_227_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_227_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_227_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_56_COEFF_PROBS_227_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_OFFSET	(0x0CD8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_57, COEFF_PROBS_228
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_228_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_228_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_228_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_228_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_57, COEFF_PROBS_229
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_229_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_229_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_229_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_229_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_57, COEFF_PROBS_230
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_230_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_230_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_230_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_230_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_57, COEFF_PROBS_231
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_231_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_231_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_231_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_57_COEFF_PROBS_231_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_OFFSET	(0x0CDC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_58, COEFF_PROBS_232
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_232_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_232_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_232_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_232_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_58, COEFF_PROBS_233
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_233_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_233_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_233_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_233_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_58, COEFF_PROBS_234
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_234_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_234_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_234_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_234_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_58, COEFF_PROBS_235
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_235_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_235_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_235_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_58_COEFF_PROBS_235_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_OFFSET	(0x0CE0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_59, COEFF_PROBS_236
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_236_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_236_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_236_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_236_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_59, COEFF_PROBS_237
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_237_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_237_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_237_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_237_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_59, COEFF_PROBS_238
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_238_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_238_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_238_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_238_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_59, COEFF_PROBS_239
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_239_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_239_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_239_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_59_COEFF_PROBS_239_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_OFFSET	(0x0CE4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_60, COEFF_PROBS_240
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_240_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_240_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_240_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_240_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_60, COEFF_PROBS_241
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_241_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_241_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_241_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_241_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_60, COEFF_PROBS_242
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_242_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_242_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_242_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_242_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_60, COEFF_PROBS_243
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_243_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_243_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_243_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_60_COEFF_PROBS_243_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_OFFSET	(0x0CE8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_61, COEFF_PROBS_244
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_244_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_244_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_244_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_244_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_61, COEFF_PROBS_245
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_245_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_245_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_245_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_245_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_61, COEFF_PROBS_246
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_246_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_246_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_246_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_246_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_61, COEFF_PROBS_247
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_247_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_247_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_247_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_61_COEFF_PROBS_247_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_OFFSET	(0x0CEC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_62, COEFF_PROBS_248
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_248_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_248_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_248_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_248_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_62, COEFF_PROBS_249
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_249_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_249_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_249_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_249_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_62, COEFF_PROBS_250
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_250_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_250_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_250_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_250_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_62, COEFF_PROBS_251
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_251_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_251_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_251_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_62_COEFF_PROBS_251_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_OFFSET	(0x0CF0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_63, COEFF_PROBS_252
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_252_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_252_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_252_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_252_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_63, COEFF_PROBS_253
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_253_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_253_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_253_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_253_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_63, COEFF_PROBS_254
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_254_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_254_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_254_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_254_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_63, COEFF_PROBS_255
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_255_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_255_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_255_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_63_COEFF_PROBS_255_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_OFFSET	(0x0CF4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_64, COEFF_PROBS_256
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_256_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_256_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_256_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_256_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_64, COEFF_PROBS_257
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_257_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_257_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_257_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_257_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_64, COEFF_PROBS_258
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_258_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_258_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_258_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_258_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_64, COEFF_PROBS_259
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_259_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_259_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_259_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_64_COEFF_PROBS_259_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_OFFSET	(0x0CF8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_65, COEFF_PROBS_260
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_260_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_260_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_260_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_260_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_65, COEFF_PROBS_261
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_261_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_261_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_261_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_261_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_65, COEFF_PROBS_262
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_262_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_262_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_262_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_262_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_65, COEFF_PROBS_263
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_263_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_263_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_263_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_65_COEFF_PROBS_263_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_OFFSET	(0x0CFC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_66, COEFF_PROBS_264
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_264_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_264_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_264_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_264_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_66, COEFF_PROBS_265
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_265_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_265_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_265_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_265_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_66, COEFF_PROBS_266
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_266_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_266_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_266_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_266_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_66, COEFF_PROBS_267
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_267_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_267_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_267_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_66_COEFF_PROBS_267_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_OFFSET	(0x0D00)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_67, COEFF_PROBS_268
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_268_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_268_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_268_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_268_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_67, COEFF_PROBS_269
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_269_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_269_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_269_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_269_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_67, COEFF_PROBS_270
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_270_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_270_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_270_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_270_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_67, COEFF_PROBS_271
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_271_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_271_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_271_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_67_COEFF_PROBS_271_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_OFFSET	(0x0D04)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_68, COEFF_PROBS_272
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_272_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_272_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_272_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_272_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_68, COEFF_PROBS_273
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_273_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_273_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_273_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_273_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_68, COEFF_PROBS_274
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_274_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_274_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_274_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_274_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_68, COEFF_PROBS_275
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_275_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_275_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_275_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_68_COEFF_PROBS_275_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_OFFSET	(0x0D08)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_69, COEFF_PROBS_276
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_276_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_276_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_276_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_276_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_69, COEFF_PROBS_277
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_277_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_277_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_277_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_277_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_69, COEFF_PROBS_278
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_278_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_278_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_278_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_278_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_69, COEFF_PROBS_279
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_279_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_279_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_279_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_69_COEFF_PROBS_279_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_OFFSET	(0x0D0C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_70, COEFF_PROBS_280
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_280_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_280_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_280_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_280_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_70, COEFF_PROBS_281
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_281_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_281_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_281_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_281_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_70, COEFF_PROBS_282
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_282_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_282_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_282_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_282_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_70, COEFF_PROBS_283
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_283_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_283_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_283_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_70_COEFF_PROBS_283_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_OFFSET	(0x0D10)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_71, COEFF_PROBS_284
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_284_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_284_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_284_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_284_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_71, COEFF_PROBS_285
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_285_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_285_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_285_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_285_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_71, COEFF_PROBS_286
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_286_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_286_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_286_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_286_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_71, COEFF_PROBS_287
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_287_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_287_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_287_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_71_COEFF_PROBS_287_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_OFFSET	(0x0D14)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_72, COEFF_PROBS_288
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_288_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_288_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_288_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_288_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_72, COEFF_PROBS_289
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_289_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_289_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_289_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_289_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_72, COEFF_PROBS_290
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_290_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_290_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_290_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_290_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_72, COEFF_PROBS_291
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_291_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_291_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_291_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_72_COEFF_PROBS_291_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_OFFSET	(0x0D18)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_73, COEFF_PROBS_292
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_292_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_292_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_292_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_292_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_73, COEFF_PROBS_293
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_293_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_293_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_293_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_293_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_73, COEFF_PROBS_294
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_294_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_294_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_294_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_294_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_73, COEFF_PROBS_295
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_295_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_295_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_295_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_73_COEFF_PROBS_295_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_OFFSET	(0x0D1C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_74, COEFF_PROBS_296
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_296_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_296_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_296_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_296_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_74, COEFF_PROBS_297
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_297_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_297_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_297_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_297_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_74, COEFF_PROBS_298
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_298_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_298_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_298_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_298_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_74, COEFF_PROBS_299
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_299_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_299_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_299_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_74_COEFF_PROBS_299_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_OFFSET	(0x0D20)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_75, COEFF_PROBS_300
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_300_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_300_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_300_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_300_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_75, COEFF_PROBS_301
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_301_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_301_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_301_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_301_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_75, COEFF_PROBS_302
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_302_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_302_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_302_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_302_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_75, COEFF_PROBS_303
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_303_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_303_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_303_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_75_COEFF_PROBS_303_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_OFFSET	(0x0D24)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_76, COEFF_PROBS_304
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_304_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_304_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_304_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_304_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_76, COEFF_PROBS_305
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_305_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_305_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_305_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_305_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_76, COEFF_PROBS_306
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_306_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_306_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_306_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_306_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_76, COEFF_PROBS_307
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_307_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_307_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_307_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_76_COEFF_PROBS_307_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_OFFSET	(0x0D28)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_77, COEFF_PROBS_308
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_308_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_308_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_308_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_308_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_77, COEFF_PROBS_309
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_309_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_309_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_309_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_309_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_77, COEFF_PROBS_310
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_310_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_310_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_310_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_310_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_77, COEFF_PROBS_311
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_311_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_311_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_311_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_77_COEFF_PROBS_311_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_OFFSET	(0x0D2C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_78, COEFF_PROBS_312
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_312_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_312_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_312_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_312_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_78, COEFF_PROBS_313
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_313_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_313_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_313_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_313_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_78, COEFF_PROBS_314
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_314_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_314_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_314_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_314_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_78, COEFF_PROBS_315
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_315_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_315_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_315_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_78_COEFF_PROBS_315_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_OFFSET	(0x0D30)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_79, COEFF_PROBS_316
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_316_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_316_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_316_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_316_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_79, COEFF_PROBS_317
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_317_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_317_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_317_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_317_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_79, COEFF_PROBS_318
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_318_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_318_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_318_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_318_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_79, COEFF_PROBS_319
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_319_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_319_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_319_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_79_COEFF_PROBS_319_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_OFFSET	(0x0D34)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_80, COEFF_PROBS_320
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_320_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_320_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_320_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_320_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_80, COEFF_PROBS_321
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_321_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_321_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_321_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_321_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_80, COEFF_PROBS_322
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_322_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_322_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_322_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_322_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_80, COEFF_PROBS_323
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_323_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_323_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_323_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_80_COEFF_PROBS_323_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_OFFSET	(0x0D38)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_81, COEFF_PROBS_324
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_324_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_324_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_324_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_324_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_81, COEFF_PROBS_325
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_325_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_325_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_325_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_325_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_81, COEFF_PROBS_326
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_326_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_326_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_326_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_326_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_81, COEFF_PROBS_327
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_327_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_327_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_327_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_81_COEFF_PROBS_327_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_OFFSET	(0x0D3C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_82, COEFF_PROBS_328
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_328_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_328_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_328_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_328_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_82, COEFF_PROBS_329
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_329_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_329_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_329_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_329_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_82, COEFF_PROBS_330
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_330_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_330_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_330_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_330_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_82, COEFF_PROBS_331
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_331_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_331_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_331_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_82_COEFF_PROBS_331_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_OFFSET	(0x0D40)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_83, COEFF_PROBS_332
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_332_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_332_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_332_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_332_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_83, COEFF_PROBS_333
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_333_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_333_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_333_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_333_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_83, COEFF_PROBS_334
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_334_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_334_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_334_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_334_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_83, COEFF_PROBS_335
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_335_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_335_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_335_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_83_COEFF_PROBS_335_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_OFFSET	(0x0D44)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_84, COEFF_PROBS_336
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_336_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_336_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_336_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_336_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_84, COEFF_PROBS_337
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_337_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_337_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_337_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_337_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_84, COEFF_PROBS_338
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_338_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_338_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_338_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_338_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_84, COEFF_PROBS_339
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_339_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_339_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_339_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_84_COEFF_PROBS_339_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_OFFSET	(0x0D48)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_85, COEFF_PROBS_340
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_340_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_340_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_340_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_340_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_85, COEFF_PROBS_341
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_341_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_341_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_341_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_341_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_85, COEFF_PROBS_342
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_342_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_342_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_342_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_342_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_85, COEFF_PROBS_343
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_343_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_343_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_343_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_85_COEFF_PROBS_343_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_OFFSET	(0x0D4C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_86, COEFF_PROBS_344
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_344_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_344_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_344_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_344_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_86, COEFF_PROBS_345
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_345_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_345_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_345_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_345_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_86, COEFF_PROBS_346
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_346_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_346_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_346_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_346_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_86, COEFF_PROBS_347
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_347_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_347_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_347_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_86_COEFF_PROBS_347_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_OFFSET	(0x0D50)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_87, COEFF_PROBS_348
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_348_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_348_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_348_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_348_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_87, COEFF_PROBS_349
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_349_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_349_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_349_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_349_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_87, COEFF_PROBS_350
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_350_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_350_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_350_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_350_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_87, COEFF_PROBS_351
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_351_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_351_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_351_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_87_COEFF_PROBS_351_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_OFFSET	(0x0D54)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_88, COEFF_PROBS_352
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_352_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_352_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_352_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_352_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_88, COEFF_PROBS_353
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_353_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_353_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_353_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_353_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_88, COEFF_PROBS_354
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_354_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_354_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_354_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_354_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_88, COEFF_PROBS_355
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_355_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_355_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_355_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_88_COEFF_PROBS_355_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_OFFSET	(0x0D58)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_89, COEFF_PROBS_356
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_356_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_356_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_356_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_356_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_89, COEFF_PROBS_357
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_357_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_357_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_357_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_357_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_89, COEFF_PROBS_358
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_358_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_358_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_358_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_358_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_89, COEFF_PROBS_359
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_359_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_359_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_359_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_89_COEFF_PROBS_359_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_OFFSET	(0x0D5C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_90, COEFF_PROBS_360
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_360_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_360_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_360_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_360_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_90, COEFF_PROBS_361
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_361_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_361_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_361_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_361_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_90, COEFF_PROBS_362
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_362_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_362_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_362_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_362_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_90, COEFF_PROBS_363
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_363_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_363_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_363_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_90_COEFF_PROBS_363_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_OFFSET	(0x0D60)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_91, COEFF_PROBS_364
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_364_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_364_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_364_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_364_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_91, COEFF_PROBS_365
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_365_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_365_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_365_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_365_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_91, COEFF_PROBS_366
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_366_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_366_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_366_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_366_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_91, COEFF_PROBS_367
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_367_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_367_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_367_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_91_COEFF_PROBS_367_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_OFFSET	(0x0D64)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_92, COEFF_PROBS_368
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_368_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_368_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_368_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_368_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_92, COEFF_PROBS_369
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_369_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_369_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_369_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_369_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_92, COEFF_PROBS_370
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_370_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_370_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_370_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_370_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_92, COEFF_PROBS_371
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_371_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_371_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_371_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_92_COEFF_PROBS_371_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_OFFSET	(0x0D68)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_93, COEFF_PROBS_372
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_372_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_372_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_372_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_372_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_93, COEFF_PROBS_373
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_373_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_373_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_373_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_373_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_93, COEFF_PROBS_374
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_374_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_374_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_374_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_374_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_93, COEFF_PROBS_375
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_375_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_375_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_375_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_93_COEFF_PROBS_375_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_OFFSET	(0x0D6C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_94, COEFF_PROBS_376
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_376_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_376_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_376_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_376_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_94, COEFF_PROBS_377
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_377_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_377_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_377_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_377_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_94, COEFF_PROBS_378
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_378_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_378_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_378_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_378_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_94, COEFF_PROBS_379
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_379_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_379_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_379_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_94_COEFF_PROBS_379_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_OFFSET	(0x0D70)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_95, COEFF_PROBS_380
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_380_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_380_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_380_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_380_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_95, COEFF_PROBS_381
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_381_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_381_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_381_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_381_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_95, COEFF_PROBS_382
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_382_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_382_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_382_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_382_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_95, COEFF_PROBS_383
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_383_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_383_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_383_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_95_COEFF_PROBS_383_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_OFFSET	(0x0D74)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_96, COEFF_PROBS_384
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_384_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_384_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_384_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_384_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_96, COEFF_PROBS_385
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_385_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_385_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_385_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_385_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_96, COEFF_PROBS_386
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_386_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_386_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_386_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_386_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_96, COEFF_PROBS_387
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_387_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_387_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_387_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_96_COEFF_PROBS_387_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_OFFSET	(0x0D78)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_97, COEFF_PROBS_388
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_388_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_388_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_388_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_388_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_97, COEFF_PROBS_389
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_389_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_389_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_389_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_389_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_97, COEFF_PROBS_390
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_390_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_390_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_390_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_390_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_97, COEFF_PROBS_391
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_391_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_391_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_391_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_97_COEFF_PROBS_391_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_OFFSET	(0x0D7C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_98, COEFF_PROBS_392
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_392_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_392_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_392_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_392_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_98, COEFF_PROBS_393
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_393_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_393_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_393_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_393_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_98, COEFF_PROBS_394
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_394_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_394_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_394_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_394_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_98, COEFF_PROBS_395
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_395_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_395_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_395_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_98_COEFF_PROBS_395_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_OFFSET	(0x0D80)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_99, COEFF_PROBS_396
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_396_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_396_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_396_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_396_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_99, COEFF_PROBS_397
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_397_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_397_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_397_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_397_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_99, COEFF_PROBS_398
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_398_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_398_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_398_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_398_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_99, COEFF_PROBS_399
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_399_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_399_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_399_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_99_COEFF_PROBS_399_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_OFFSET	(0x0D84)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_100, COEFF_PROBS_400
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_400_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_400_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_400_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_400_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_100, COEFF_PROBS_401
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_401_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_401_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_401_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_401_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_100, COEFF_PROBS_402
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_402_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_402_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_402_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_402_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_100, COEFF_PROBS_403
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_403_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_403_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_403_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_100_COEFF_PROBS_403_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_OFFSET	(0x0D88)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_101, COEFF_PROBS_404
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_404_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_404_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_404_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_404_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_101, COEFF_PROBS_405
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_405_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_405_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_405_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_405_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_101, COEFF_PROBS_406
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_406_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_406_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_406_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_406_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_101, COEFF_PROBS_407
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_407_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_407_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_407_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_101_COEFF_PROBS_407_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_OFFSET	(0x0D8C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_102, COEFF_PROBS_408
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_408_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_408_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_408_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_408_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_102, COEFF_PROBS_409
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_409_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_409_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_409_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_409_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_102, COEFF_PROBS_410
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_410_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_410_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_410_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_410_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_102, COEFF_PROBS_411
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_411_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_411_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_411_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_102_COEFF_PROBS_411_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_OFFSET	(0x0D90)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_103, COEFF_PROBS_412
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_412_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_412_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_412_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_412_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_103, COEFF_PROBS_413
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_413_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_413_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_413_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_413_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_103, COEFF_PROBS_414
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_414_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_414_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_414_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_414_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_103, COEFF_PROBS_415
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_415_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_415_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_415_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_103_COEFF_PROBS_415_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_OFFSET	(0x0D94)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_104, COEFF_PROBS_416
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_416_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_416_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_416_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_416_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_104, COEFF_PROBS_417
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_417_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_417_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_417_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_417_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_104, COEFF_PROBS_418
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_418_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_418_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_418_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_418_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_104, COEFF_PROBS_419
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_419_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_419_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_419_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_104_COEFF_PROBS_419_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_OFFSET	(0x0D98)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_105, COEFF_PROBS_420
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_420_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_420_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_420_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_420_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_105, COEFF_PROBS_421
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_421_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_421_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_421_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_421_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_105, COEFF_PROBS_422
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_422_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_422_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_422_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_422_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_105, COEFF_PROBS_423
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_423_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_423_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_423_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_105_COEFF_PROBS_423_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_OFFSET	(0x0D9C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_106, COEFF_PROBS_424
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_424_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_424_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_424_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_424_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_106, COEFF_PROBS_425
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_425_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_425_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_425_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_425_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_106, COEFF_PROBS_426
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_426_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_426_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_426_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_426_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_106, COEFF_PROBS_427
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_427_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_427_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_427_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_106_COEFF_PROBS_427_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_OFFSET	(0x0DA0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_107, COEFF_PROBS_428
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_428_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_428_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_428_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_428_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_107, COEFF_PROBS_429
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_429_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_429_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_429_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_429_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_107, COEFF_PROBS_430
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_430_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_430_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_430_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_430_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_107, COEFF_PROBS_431
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_431_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_431_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_431_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_107_COEFF_PROBS_431_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_OFFSET	(0x0DA4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_108, COEFF_PROBS_432
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_432_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_432_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_432_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_432_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_108, COEFF_PROBS_433
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_433_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_433_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_433_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_433_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_108, COEFF_PROBS_434
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_434_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_434_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_434_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_434_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_108, COEFF_PROBS_435
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_435_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_435_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_435_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_108_COEFF_PROBS_435_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_OFFSET	(0x0DA8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_109, COEFF_PROBS_436
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_436_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_436_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_436_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_436_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_109, COEFF_PROBS_437
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_437_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_437_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_437_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_437_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_109, COEFF_PROBS_438
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_438_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_438_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_438_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_438_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_109, COEFF_PROBS_439
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_439_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_439_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_439_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_109_COEFF_PROBS_439_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_OFFSET	(0x0DAC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_110, COEFF_PROBS_440
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_440_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_440_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_440_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_440_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_110, COEFF_PROBS_441
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_441_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_441_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_441_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_441_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_110, COEFF_PROBS_442
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_442_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_442_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_442_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_442_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_110, COEFF_PROBS_443
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_443_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_443_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_443_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_110_COEFF_PROBS_443_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_OFFSET	(0x0DB0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_111, COEFF_PROBS_444
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_444_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_444_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_444_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_444_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_111, COEFF_PROBS_445
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_445_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_445_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_445_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_445_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_111, COEFF_PROBS_446
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_446_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_446_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_446_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_446_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_111, COEFF_PROBS_447
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_447_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_447_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_447_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_111_COEFF_PROBS_447_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_OFFSET	(0x0DB4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_112, COEFF_PROBS_448
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_448_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_448_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_448_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_448_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_112, COEFF_PROBS_449
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_449_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_449_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_449_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_449_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_112, COEFF_PROBS_450
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_450_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_450_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_450_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_450_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_112, COEFF_PROBS_451
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_451_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_451_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_451_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_112_COEFF_PROBS_451_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_OFFSET	(0x0DB8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_113, COEFF_PROBS_452
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_452_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_452_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_452_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_452_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_113, COEFF_PROBS_453
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_453_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_453_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_453_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_453_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_113, COEFF_PROBS_454
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_454_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_454_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_454_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_454_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_113, COEFF_PROBS_455
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_455_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_455_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_455_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_113_COEFF_PROBS_455_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_OFFSET	(0x0DBC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_114, COEFF_PROBS_456
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_456_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_456_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_456_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_456_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_114, COEFF_PROBS_457
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_457_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_457_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_457_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_457_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_114, COEFF_PROBS_458
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_458_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_458_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_458_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_458_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_114, COEFF_PROBS_459
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_459_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_459_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_459_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_114_COEFF_PROBS_459_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_OFFSET	(0x0DC0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_115, COEFF_PROBS_460
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_460_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_460_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_460_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_460_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_115, COEFF_PROBS_461
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_461_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_461_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_461_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_461_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_115, COEFF_PROBS_462
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_462_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_462_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_462_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_462_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_115, COEFF_PROBS_463
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_463_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_463_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_463_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_115_COEFF_PROBS_463_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_OFFSET	(0x0DC4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_116, COEFF_PROBS_464
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_464_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_464_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_464_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_464_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_116, COEFF_PROBS_465
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_465_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_465_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_465_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_465_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_116, COEFF_PROBS_466
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_466_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_466_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_466_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_466_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_116, COEFF_PROBS_467
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_467_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_467_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_467_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_116_COEFF_PROBS_467_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_OFFSET	(0x0DC8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_117, COEFF_PROBS_468
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_468_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_468_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_468_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_468_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_117, COEFF_PROBS_469
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_469_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_469_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_469_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_469_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_117, COEFF_PROBS_470
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_470_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_470_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_470_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_470_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_117, COEFF_PROBS_471
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_471_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_471_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_471_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_117_COEFF_PROBS_471_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_OFFSET	(0x0DCC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_118, COEFF_PROBS_472
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_472_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_472_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_472_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_472_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_118, COEFF_PROBS_473
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_473_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_473_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_473_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_473_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_118, COEFF_PROBS_474
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_474_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_474_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_474_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_474_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_118, COEFF_PROBS_475
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_475_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_475_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_475_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_118_COEFF_PROBS_475_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_OFFSET	(0x0DD0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_119, COEFF_PROBS_476
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_476_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_476_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_476_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_476_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_119, COEFF_PROBS_477
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_477_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_477_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_477_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_477_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_119, COEFF_PROBS_478
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_478_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_478_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_478_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_478_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_119, COEFF_PROBS_479
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_479_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_479_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_479_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_119_COEFF_PROBS_479_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_OFFSET	(0x0DD4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_120, COEFF_PROBS_480
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_480_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_480_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_480_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_480_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_120, COEFF_PROBS_481
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_481_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_481_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_481_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_481_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_120, COEFF_PROBS_482
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_482_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_482_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_482_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_482_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_120, COEFF_PROBS_483
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_483_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_483_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_483_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_120_COEFF_PROBS_483_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_OFFSET	(0x0DD8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_121, COEFF_PROBS_484
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_484_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_484_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_484_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_484_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_121, COEFF_PROBS_485
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_485_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_485_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_485_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_485_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_121, COEFF_PROBS_486
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_486_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_486_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_486_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_486_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_121, COEFF_PROBS_487
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_487_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_487_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_487_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_121_COEFF_PROBS_487_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_OFFSET	(0x0DDC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_122, COEFF_PROBS_488
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_488_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_488_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_488_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_488_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_122, COEFF_PROBS_489
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_489_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_489_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_489_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_489_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_122, COEFF_PROBS_490
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_490_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_490_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_490_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_490_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_122, COEFF_PROBS_491
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_491_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_491_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_491_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_122_COEFF_PROBS_491_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_OFFSET	(0x0DE0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_123, COEFF_PROBS_492
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_492_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_492_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_492_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_492_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_123, COEFF_PROBS_493
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_493_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_493_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_493_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_493_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_123, COEFF_PROBS_494
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_494_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_494_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_494_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_494_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_123, COEFF_PROBS_495
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_495_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_495_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_495_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_123_COEFF_PROBS_495_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_OFFSET	(0x0DE4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_124, COEFF_PROBS_496
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_496_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_496_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_496_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_496_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_124, COEFF_PROBS_497
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_497_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_497_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_497_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_497_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_124, COEFF_PROBS_498
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_498_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_498_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_498_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_498_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_124, COEFF_PROBS_499
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_499_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_499_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_499_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_124_COEFF_PROBS_499_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_OFFSET	(0x0DE8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_125, COEFF_PROBS_500
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_500_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_500_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_500_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_500_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_125, COEFF_PROBS_501
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_501_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_501_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_501_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_501_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_125, COEFF_PROBS_502
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_502_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_502_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_502_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_502_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_125, COEFF_PROBS_503
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_503_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_503_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_503_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_125_COEFF_PROBS_503_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_OFFSET	(0x0DEC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_126, COEFF_PROBS_504
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_504_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_504_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_504_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_504_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_126, COEFF_PROBS_505
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_505_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_505_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_505_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_505_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_126, COEFF_PROBS_506
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_506_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_506_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_506_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_506_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_126, COEFF_PROBS_507
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_507_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_507_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_507_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_126_COEFF_PROBS_507_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_OFFSET	(0x0DF0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_127, COEFF_PROBS_508
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_508_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_508_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_508_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_508_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_127, COEFF_PROBS_509
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_509_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_509_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_509_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_509_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_127, COEFF_PROBS_510
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_510_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_510_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_510_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_510_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_127, COEFF_PROBS_511
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_511_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_511_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_511_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_127_COEFF_PROBS_511_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_OFFSET	(0x0DF4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_128, COEFF_PROBS_512
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_512_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_512_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_512_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_512_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_128, COEFF_PROBS_513
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_513_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_513_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_513_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_513_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_128, COEFF_PROBS_514
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_514_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_514_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_514_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_514_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_128, COEFF_PROBS_515
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_515_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_515_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_515_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_128_COEFF_PROBS_515_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_OFFSET	(0x0DF8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_129, COEFF_PROBS_516
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_516_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_516_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_516_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_516_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_129, COEFF_PROBS_517
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_517_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_517_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_517_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_517_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_129, COEFF_PROBS_518
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_518_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_518_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_518_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_518_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_129, COEFF_PROBS_519
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_519_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_519_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_519_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_129_COEFF_PROBS_519_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_OFFSET	(0x0DFC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_130, COEFF_PROBS_520
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_520_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_520_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_520_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_520_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_130, COEFF_PROBS_521
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_521_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_521_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_521_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_521_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_130, COEFF_PROBS_522
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_522_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_522_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_522_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_522_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_130, COEFF_PROBS_523
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_523_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_523_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_523_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_130_COEFF_PROBS_523_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_OFFSET	(0x0E00)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_131, COEFF_PROBS_524
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_524_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_524_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_524_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_524_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_131, COEFF_PROBS_525
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_525_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_525_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_525_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_525_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_131, COEFF_PROBS_526
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_526_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_526_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_526_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_526_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_131, COEFF_PROBS_527
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_527_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_527_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_527_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_131_COEFF_PROBS_527_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_OFFSET	(0x0E04)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_132, COEFF_PROBS_528
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_528_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_528_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_528_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_528_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_132, COEFF_PROBS_529
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_529_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_529_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_529_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_529_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_132, COEFF_PROBS_530
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_530_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_530_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_530_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_530_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_132, COEFF_PROBS_531
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_531_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_531_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_531_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_132_COEFF_PROBS_531_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_OFFSET	(0x0E08)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_133, COEFF_PROBS_532
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_532_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_532_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_532_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_532_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_133, COEFF_PROBS_533
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_533_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_533_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_533_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_533_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_133, COEFF_PROBS_534
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_534_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_534_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_534_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_534_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_133, COEFF_PROBS_535
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_535_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_535_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_535_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_133_COEFF_PROBS_535_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_OFFSET	(0x0E0C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_134, COEFF_PROBS_536
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_536_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_536_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_536_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_536_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_134, COEFF_PROBS_537
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_537_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_537_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_537_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_537_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_134, COEFF_PROBS_538
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_538_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_538_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_538_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_538_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_134, COEFF_PROBS_539
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_539_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_539_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_539_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_134_COEFF_PROBS_539_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_OFFSET	(0x0E10)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_135, COEFF_PROBS_540
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_540_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_540_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_540_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_540_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_135, COEFF_PROBS_541
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_541_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_541_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_541_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_541_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_135, COEFF_PROBS_542
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_542_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_542_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_542_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_542_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_135, COEFF_PROBS_543
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_543_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_543_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_543_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_135_COEFF_PROBS_543_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_OFFSET	(0x0E14)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_136, COEFF_PROBS_544
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_544_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_544_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_544_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_544_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_136, COEFF_PROBS_545
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_545_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_545_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_545_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_545_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_136, COEFF_PROBS_546
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_546_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_546_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_546_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_546_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_136, COEFF_PROBS_547
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_547_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_547_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_547_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_136_COEFF_PROBS_547_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_OFFSET	(0x0E18)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_137, COEFF_PROBS_548
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_548_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_548_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_548_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_548_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_137, COEFF_PROBS_549
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_549_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_549_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_549_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_549_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_137, COEFF_PROBS_550
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_550_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_550_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_550_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_550_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_137, COEFF_PROBS_551
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_551_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_551_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_551_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_137_COEFF_PROBS_551_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_OFFSET	(0x0E1C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_138, COEFF_PROBS_552
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_552_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_552_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_552_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_552_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_138, COEFF_PROBS_553
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_553_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_553_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_553_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_553_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_138, COEFF_PROBS_554
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_554_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_554_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_554_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_554_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_138, COEFF_PROBS_555
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_555_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_555_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_555_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_138_COEFF_PROBS_555_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_OFFSET	(0x0E20)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_139, COEFF_PROBS_556
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_556_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_556_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_556_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_556_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_139, COEFF_PROBS_557
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_557_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_557_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_557_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_557_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_139, COEFF_PROBS_558
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_558_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_558_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_558_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_558_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_139, COEFF_PROBS_559
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_559_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_559_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_559_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_139_COEFF_PROBS_559_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_OFFSET	(0x0E24)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_140, COEFF_PROBS_560
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_560_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_560_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_560_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_560_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_140, COEFF_PROBS_561
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_561_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_561_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_561_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_561_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_140, COEFF_PROBS_562
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_562_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_562_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_562_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_562_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_140, COEFF_PROBS_563
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_563_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_563_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_563_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_140_COEFF_PROBS_563_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_OFFSET	(0x0E28)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_141, COEFF_PROBS_564
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_564_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_564_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_564_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_564_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_141, COEFF_PROBS_565
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_565_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_565_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_565_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_565_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_141, COEFF_PROBS_566
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_566_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_566_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_566_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_566_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_141, COEFF_PROBS_567
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_567_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_567_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_567_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_141_COEFF_PROBS_567_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_OFFSET	(0x0E2C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_142, COEFF_PROBS_568
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_568_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_568_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_568_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_568_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_142, COEFF_PROBS_569
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_569_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_569_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_569_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_569_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_142, COEFF_PROBS_570
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_570_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_570_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_570_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_570_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_142, COEFF_PROBS_571
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_571_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_571_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_571_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_142_COEFF_PROBS_571_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_OFFSET	(0x0E30)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_143, COEFF_PROBS_572
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_572_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_572_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_572_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_572_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_143, COEFF_PROBS_573
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_573_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_573_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_573_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_573_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_143, COEFF_PROBS_574
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_574_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_574_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_574_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_574_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_143, COEFF_PROBS_575
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_575_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_575_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_575_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_143_COEFF_PROBS_575_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_OFFSET	(0x0E34)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_144, COEFF_PROBS_576
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_576_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_576_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_576_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_576_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_144, COEFF_PROBS_577
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_577_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_577_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_577_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_577_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_144, COEFF_PROBS_578
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_578_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_578_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_578_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_578_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_144, COEFF_PROBS_579
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_579_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_579_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_579_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_144_COEFF_PROBS_579_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_OFFSET	(0x0E38)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_145, COEFF_PROBS_580
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_580_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_580_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_580_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_580_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_145, COEFF_PROBS_581
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_581_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_581_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_581_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_581_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_145, COEFF_PROBS_582
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_582_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_582_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_582_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_582_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_145, COEFF_PROBS_583
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_583_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_583_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_583_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_145_COEFF_PROBS_583_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_OFFSET	(0x0E3C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_146, COEFF_PROBS_584
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_584_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_584_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_584_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_584_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_146, COEFF_PROBS_585
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_585_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_585_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_585_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_585_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_146, COEFF_PROBS_586
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_586_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_586_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_586_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_586_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_146, COEFF_PROBS_587
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_587_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_587_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_587_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_146_COEFF_PROBS_587_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_OFFSET	(0x0E40)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_147, COEFF_PROBS_588
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_588_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_588_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_588_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_588_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_147, COEFF_PROBS_589
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_589_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_589_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_589_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_589_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_147, COEFF_PROBS_590
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_590_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_590_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_590_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_590_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_147, COEFF_PROBS_591
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_591_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_591_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_591_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_147_COEFF_PROBS_591_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_OFFSET	(0x0E44)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_148, COEFF_PROBS_592
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_592_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_592_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_592_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_592_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_148, COEFF_PROBS_593
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_593_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_593_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_593_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_593_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_148, COEFF_PROBS_594
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_594_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_594_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_594_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_594_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_148, COEFF_PROBS_595
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_595_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_595_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_595_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_148_COEFF_PROBS_595_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_OFFSET	(0x0E48)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_149, COEFF_PROBS_596
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_596_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_596_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_596_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_596_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_149, COEFF_PROBS_597
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_597_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_597_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_597_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_597_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_149, COEFF_PROBS_598
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_598_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_598_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_598_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_598_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_149, COEFF_PROBS_599
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_599_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_599_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_599_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_149_COEFF_PROBS_599_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_OFFSET	(0x0E4C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_150, COEFF_PROBS_600
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_600_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_600_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_600_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_600_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_150, COEFF_PROBS_601
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_601_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_601_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_601_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_601_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_150, COEFF_PROBS_602
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_602_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_602_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_602_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_602_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_150, COEFF_PROBS_603
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_603_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_603_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_603_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_150_COEFF_PROBS_603_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_OFFSET	(0x0E50)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_151, COEFF_PROBS_604
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_604_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_604_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_604_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_604_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_151, COEFF_PROBS_605
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_605_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_605_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_605_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_605_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_151, COEFF_PROBS_606
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_606_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_606_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_606_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_606_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_151, COEFF_PROBS_607
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_607_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_607_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_607_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_151_COEFF_PROBS_607_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_OFFSET	(0x0E54)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_152, COEFF_PROBS_608
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_608_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_608_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_608_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_608_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_152, COEFF_PROBS_609
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_609_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_609_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_609_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_609_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_152, COEFF_PROBS_610
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_610_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_610_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_610_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_610_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_152, COEFF_PROBS_611
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_611_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_611_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_611_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_152_COEFF_PROBS_611_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_OFFSET	(0x0E58)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_153, COEFF_PROBS_612
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_612_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_612_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_612_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_612_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_153, COEFF_PROBS_613
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_613_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_613_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_613_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_613_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_153, COEFF_PROBS_614
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_614_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_614_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_614_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_614_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_153, COEFF_PROBS_615
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_615_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_615_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_615_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_153_COEFF_PROBS_615_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_OFFSET	(0x0E5C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_154, COEFF_PROBS_616
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_616_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_616_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_616_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_616_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_154, COEFF_PROBS_617
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_617_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_617_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_617_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_617_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_154, COEFF_PROBS_618
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_618_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_618_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_618_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_618_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_154, COEFF_PROBS_619
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_619_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_619_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_619_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_154_COEFF_PROBS_619_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_OFFSET	(0x0E60)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_155, COEFF_PROBS_620
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_620_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_620_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_620_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_620_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_155, COEFF_PROBS_621
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_621_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_621_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_621_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_621_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_155, COEFF_PROBS_622
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_622_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_622_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_622_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_622_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_155, COEFF_PROBS_623
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_623_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_623_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_623_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_155_COEFF_PROBS_623_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_OFFSET	(0x0E64)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_156, COEFF_PROBS_624
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_624_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_624_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_624_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_624_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_156, COEFF_PROBS_625
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_625_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_625_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_625_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_625_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_156, COEFF_PROBS_626
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_626_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_626_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_626_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_626_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_156, COEFF_PROBS_627
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_627_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_627_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_627_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_156_COEFF_PROBS_627_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_OFFSET	(0x0E68)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_157, COEFF_PROBS_628
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_628_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_628_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_628_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_628_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_157, COEFF_PROBS_629
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_629_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_629_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_629_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_629_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_157, COEFF_PROBS_630
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_630_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_630_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_630_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_630_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_157, COEFF_PROBS_631
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_631_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_631_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_631_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_157_COEFF_PROBS_631_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_OFFSET	(0x0E6C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_158, COEFF_PROBS_632
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_632_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_632_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_632_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_632_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_158, COEFF_PROBS_633
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_633_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_633_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_633_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_633_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_158, COEFF_PROBS_634
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_634_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_634_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_634_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_634_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_158, COEFF_PROBS_635
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_635_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_635_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_635_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_158_COEFF_PROBS_635_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_OFFSET	(0x0E70)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_159, COEFF_PROBS_636
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_636_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_636_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_636_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_636_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_159, COEFF_PROBS_637
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_637_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_637_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_637_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_637_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_159, COEFF_PROBS_638
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_638_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_638_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_638_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_638_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_159, COEFF_PROBS_639
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_639_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_639_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_639_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_159_COEFF_PROBS_639_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_OFFSET	(0x0E74)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_160, COEFF_PROBS_640
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_640_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_640_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_640_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_640_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_160, COEFF_PROBS_641
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_641_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_641_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_641_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_641_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_160, COEFF_PROBS_642
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_642_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_642_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_642_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_642_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_160, COEFF_PROBS_643
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_643_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_643_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_643_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_160_COEFF_PROBS_643_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_OFFSET	(0x0E78)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_161, COEFF_PROBS_644
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_644_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_644_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_644_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_644_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_161, COEFF_PROBS_645
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_645_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_645_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_645_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_645_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_161, COEFF_PROBS_646
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_646_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_646_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_646_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_646_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_161, COEFF_PROBS_647
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_647_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_647_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_647_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_161_COEFF_PROBS_647_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_OFFSET	(0x0E7C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_162, COEFF_PROBS_648
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_648_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_648_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_648_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_648_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_162, COEFF_PROBS_649
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_649_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_649_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_649_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_649_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_162, COEFF_PROBS_650
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_650_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_650_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_650_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_650_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_162, COEFF_PROBS_651
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_651_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_651_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_651_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_162_COEFF_PROBS_651_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_OFFSET	(0x0E80)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_163, COEFF_PROBS_652
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_652_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_652_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_652_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_652_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_163, COEFF_PROBS_653
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_653_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_653_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_653_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_653_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_163, COEFF_PROBS_654
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_654_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_654_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_654_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_654_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_163, COEFF_PROBS_655
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_655_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_655_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_655_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_163_COEFF_PROBS_655_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_OFFSET	(0x0E84)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_164, COEFF_PROBS_656
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_656_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_656_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_656_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_656_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_164, COEFF_PROBS_657
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_657_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_657_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_657_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_657_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_164, COEFF_PROBS_658
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_658_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_658_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_658_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_658_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_164, COEFF_PROBS_659
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_659_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_659_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_659_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_164_COEFF_PROBS_659_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_OFFSET	(0x0E88)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_165, COEFF_PROBS_660
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_660_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_660_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_660_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_660_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_165, COEFF_PROBS_661
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_661_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_661_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_661_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_661_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_165, COEFF_PROBS_662
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_662_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_662_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_662_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_662_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_165, COEFF_PROBS_663
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_663_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_663_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_663_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_165_COEFF_PROBS_663_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_OFFSET	(0x0E8C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_166, COEFF_PROBS_664
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_664_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_664_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_664_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_664_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_166, COEFF_PROBS_665
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_665_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_665_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_665_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_665_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_166, COEFF_PROBS_666
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_666_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_666_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_666_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_666_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_166, COEFF_PROBS_667
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_667_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_667_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_667_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_166_COEFF_PROBS_667_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_OFFSET	(0x0E90)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_167, COEFF_PROBS_668
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_668_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_668_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_668_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_668_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_167, COEFF_PROBS_669
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_669_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_669_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_669_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_669_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_167, COEFF_PROBS_670
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_670_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_670_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_670_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_670_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_167, COEFF_PROBS_671
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_671_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_671_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_671_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_167_COEFF_PROBS_671_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_OFFSET	(0x0E94)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_168, COEFF_PROBS_672
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_672_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_672_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_672_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_672_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_168, COEFF_PROBS_673
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_673_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_673_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_673_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_673_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_168, COEFF_PROBS_674
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_674_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_674_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_674_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_674_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_168, COEFF_PROBS_675
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_675_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_675_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_675_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_168_COEFF_PROBS_675_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_OFFSET	(0x0E98)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_169, COEFF_PROBS_676
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_676_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_676_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_676_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_676_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_169, COEFF_PROBS_677
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_677_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_677_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_677_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_677_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_169, COEFF_PROBS_678
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_678_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_678_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_678_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_678_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_169, COEFF_PROBS_679
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_679_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_679_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_679_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_169_COEFF_PROBS_679_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_OFFSET	(0x0E9C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_170, COEFF_PROBS_680
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_680_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_680_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_680_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_680_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_170, COEFF_PROBS_681
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_681_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_681_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_681_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_681_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_170, COEFF_PROBS_682
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_682_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_682_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_682_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_682_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_170, COEFF_PROBS_683
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_683_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_683_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_683_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_170_COEFF_PROBS_683_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_OFFSET	(0x0EA0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_171, COEFF_PROBS_684
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_684_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_684_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_684_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_684_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_171, COEFF_PROBS_685
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_685_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_685_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_685_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_685_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_171, COEFF_PROBS_686
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_686_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_686_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_686_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_686_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_171, COEFF_PROBS_687
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_687_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_687_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_687_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_171_COEFF_PROBS_687_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_OFFSET	(0x0EA4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_172, COEFF_PROBS_688
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_688_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_688_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_688_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_688_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_172, COEFF_PROBS_689
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_689_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_689_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_689_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_689_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_172, COEFF_PROBS_690
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_690_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_690_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_690_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_690_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_172, COEFF_PROBS_691
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_691_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_691_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_691_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_172_COEFF_PROBS_691_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_OFFSET	(0x0EA8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_173, COEFF_PROBS_692
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_692_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_692_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_692_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_692_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_173, COEFF_PROBS_693
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_693_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_693_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_693_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_693_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_173, COEFF_PROBS_694
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_694_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_694_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_694_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_694_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_173, COEFF_PROBS_695
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_695_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_695_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_695_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_173_COEFF_PROBS_695_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_OFFSET	(0x0EAC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_174, COEFF_PROBS_696
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_696_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_696_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_696_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_696_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_174, COEFF_PROBS_697
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_697_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_697_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_697_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_697_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_174, COEFF_PROBS_698
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_698_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_698_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_698_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_698_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_174, COEFF_PROBS_699
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_699_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_699_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_699_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_174_COEFF_PROBS_699_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_OFFSET	(0x0EB0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_175, COEFF_PROBS_700
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_700_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_700_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_700_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_700_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_175, COEFF_PROBS_701
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_701_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_701_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_701_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_701_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_175, COEFF_PROBS_702
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_702_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_702_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_702_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_702_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_175, COEFF_PROBS_703
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_703_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_703_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_703_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_175_COEFF_PROBS_703_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_OFFSET	(0x0EB4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_176, COEFF_PROBS_704
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_704_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_704_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_704_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_704_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_176, COEFF_PROBS_705
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_705_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_705_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_705_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_705_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_176, COEFF_PROBS_706
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_706_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_706_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_706_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_706_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_176, COEFF_PROBS_707
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_707_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_707_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_707_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_176_COEFF_PROBS_707_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_OFFSET	(0x0EB8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_177, COEFF_PROBS_708
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_708_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_708_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_708_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_708_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_177, COEFF_PROBS_709
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_709_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_709_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_709_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_709_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_177, COEFF_PROBS_710
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_710_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_710_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_710_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_710_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_177, COEFF_PROBS_711
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_711_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_711_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_711_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_177_COEFF_PROBS_711_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_OFFSET	(0x0EBC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_178, COEFF_PROBS_712
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_712_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_712_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_712_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_712_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_178, COEFF_PROBS_713
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_713_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_713_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_713_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_713_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_178, COEFF_PROBS_714
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_714_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_714_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_714_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_714_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_178, COEFF_PROBS_715
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_715_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_715_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_715_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_178_COEFF_PROBS_715_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_OFFSET	(0x0EC0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_179, COEFF_PROBS_716
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_716_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_716_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_716_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_716_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_179, COEFF_PROBS_717
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_717_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_717_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_717_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_717_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_179, COEFF_PROBS_718
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_718_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_718_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_718_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_718_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_179, COEFF_PROBS_719
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_719_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_719_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_719_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_179_COEFF_PROBS_719_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_OFFSET	(0x0EC4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_180, COEFF_PROBS_720
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_720_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_720_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_720_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_720_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_180, COEFF_PROBS_721
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_721_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_721_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_721_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_721_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_180, COEFF_PROBS_722
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_722_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_722_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_722_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_722_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_180, COEFF_PROBS_723
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_723_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_723_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_723_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_180_COEFF_PROBS_723_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_OFFSET	(0x0EC8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_181, COEFF_PROBS_724
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_724_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_724_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_724_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_724_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_181, COEFF_PROBS_725
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_725_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_725_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_725_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_725_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_181, COEFF_PROBS_726
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_726_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_726_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_726_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_726_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_181, COEFF_PROBS_727
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_727_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_727_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_727_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_181_COEFF_PROBS_727_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_OFFSET	(0x0ECC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_182, COEFF_PROBS_728
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_728_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_728_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_728_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_728_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_182, COEFF_PROBS_729
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_729_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_729_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_729_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_729_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_182, COEFF_PROBS_730
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_730_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_730_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_730_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_730_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_182, COEFF_PROBS_731
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_731_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_731_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_731_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_182_COEFF_PROBS_731_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_OFFSET	(0x0ED0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_183, COEFF_PROBS_732
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_732_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_732_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_732_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_732_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_183, COEFF_PROBS_733
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_733_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_733_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_733_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_733_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_183, COEFF_PROBS_734
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_734_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_734_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_734_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_734_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_183, COEFF_PROBS_735
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_735_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_735_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_735_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_183_COEFF_PROBS_735_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_OFFSET	(0x0ED4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_184, COEFF_PROBS_736
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_736_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_736_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_736_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_736_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_184, COEFF_PROBS_737
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_737_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_737_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_737_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_737_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_184, COEFF_PROBS_738
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_738_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_738_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_738_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_738_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_184, COEFF_PROBS_739
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_739_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_739_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_739_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_184_COEFF_PROBS_739_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_OFFSET	(0x0ED8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_185, COEFF_PROBS_740
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_740_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_740_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_740_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_740_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_185, COEFF_PROBS_741
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_741_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_741_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_741_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_741_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_185, COEFF_PROBS_742
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_742_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_742_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_742_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_742_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_185, COEFF_PROBS_743
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_743_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_743_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_743_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_185_COEFF_PROBS_743_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_OFFSET	(0x0EDC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_186, COEFF_PROBS_744
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_744_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_744_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_744_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_744_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_186, COEFF_PROBS_745
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_745_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_745_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_745_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_745_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_186, COEFF_PROBS_746
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_746_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_746_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_746_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_746_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_186, COEFF_PROBS_747
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_747_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_747_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_747_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_186_COEFF_PROBS_747_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_OFFSET	(0x0EE0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_187, COEFF_PROBS_748
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_748_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_748_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_748_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_748_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_187, COEFF_PROBS_749
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_749_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_749_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_749_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_749_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_187, COEFF_PROBS_750
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_750_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_750_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_750_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_750_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_187, COEFF_PROBS_751
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_751_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_751_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_751_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_187_COEFF_PROBS_751_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_OFFSET	(0x0EE4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_188, COEFF_PROBS_752
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_752_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_752_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_752_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_752_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_188, COEFF_PROBS_753
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_753_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_753_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_753_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_753_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_188, COEFF_PROBS_754
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_754_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_754_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_754_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_754_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_188, COEFF_PROBS_755
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_755_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_755_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_755_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_188_COEFF_PROBS_755_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_OFFSET	(0x0EE8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_189, COEFF_PROBS_756
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_756_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_756_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_756_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_756_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_189, COEFF_PROBS_757
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_757_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_757_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_757_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_757_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_189, COEFF_PROBS_758
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_758_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_758_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_758_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_758_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_189, COEFF_PROBS_759
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_759_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_759_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_759_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_189_COEFF_PROBS_759_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_OFFSET	(0x0EEC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_190, COEFF_PROBS_760
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_760_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_760_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_760_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_760_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_190, COEFF_PROBS_761
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_761_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_761_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_761_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_761_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_190, COEFF_PROBS_762
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_762_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_762_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_762_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_762_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_190, COEFF_PROBS_763
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_763_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_763_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_763_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_190_COEFF_PROBS_763_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_OFFSET	(0x0EF0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_191, COEFF_PROBS_764
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_764_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_764_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_764_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_764_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_191, COEFF_PROBS_765
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_765_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_765_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_765_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_765_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_191, COEFF_PROBS_766
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_766_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_766_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_766_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_766_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_191, COEFF_PROBS_767
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_767_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_767_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_767_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_191_COEFF_PROBS_767_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_OFFSET	(0x0EF4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_192, COEFF_PROBS_768
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_768_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_768_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_768_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_768_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_192, COEFF_PROBS_769
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_769_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_769_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_769_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_769_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_192, COEFF_PROBS_770
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_770_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_770_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_770_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_770_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_192, COEFF_PROBS_771
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_771_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_771_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_771_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_192_COEFF_PROBS_771_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_OFFSET	(0x0EF8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_193, COEFF_PROBS_772
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_772_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_772_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_772_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_772_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_193, COEFF_PROBS_773
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_773_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_773_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_773_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_773_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_193, COEFF_PROBS_774
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_774_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_774_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_774_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_774_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_193, COEFF_PROBS_775
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_775_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_775_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_775_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_193_COEFF_PROBS_775_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_OFFSET	(0x0EFC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_194, COEFF_PROBS_776
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_776_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_776_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_776_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_776_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_194, COEFF_PROBS_777
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_777_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_777_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_777_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_777_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_194, COEFF_PROBS_778
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_778_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_778_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_778_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_778_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_194, COEFF_PROBS_779
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_779_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_779_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_779_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_194_COEFF_PROBS_779_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_OFFSET	(0x0F00)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_195, COEFF_PROBS_780
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_780_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_780_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_780_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_780_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_195, COEFF_PROBS_781
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_781_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_781_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_781_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_781_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_195, COEFF_PROBS_782
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_782_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_782_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_782_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_782_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_195, COEFF_PROBS_783
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_783_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_783_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_783_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_195_COEFF_PROBS_783_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_OFFSET	(0x0F04)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_196, COEFF_PROBS_784
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_784_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_784_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_784_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_784_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_196, COEFF_PROBS_785
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_785_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_785_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_785_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_785_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_196, COEFF_PROBS_786
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_786_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_786_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_786_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_786_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_196, COEFF_PROBS_787
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_787_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_787_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_787_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_196_COEFF_PROBS_787_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_OFFSET	(0x0F08)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_197, COEFF_PROBS_788
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_788_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_788_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_788_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_788_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_197, COEFF_PROBS_789
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_789_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_789_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_789_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_789_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_197, COEFF_PROBS_790
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_790_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_790_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_790_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_790_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_197, COEFF_PROBS_791
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_791_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_791_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_791_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_197_COEFF_PROBS_791_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_OFFSET	(0x0F0C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_198, COEFF_PROBS_792
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_792_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_792_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_792_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_792_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_198, COEFF_PROBS_793
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_793_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_793_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_793_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_793_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_198, COEFF_PROBS_794
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_794_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_794_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_794_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_794_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_198, COEFF_PROBS_795
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_795_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_795_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_795_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_198_COEFF_PROBS_795_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_OFFSET	(0x0F10)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_199, COEFF_PROBS_796
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_796_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_796_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_796_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_796_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_199, COEFF_PROBS_797
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_797_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_797_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_797_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_797_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_199, COEFF_PROBS_798
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_798_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_798_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_798_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_798_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_199, COEFF_PROBS_799
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_799_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_799_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_799_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_199_COEFF_PROBS_799_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_OFFSET	(0x0F14)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_200, COEFF_PROBS_800
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_800_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_800_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_800_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_800_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_200, COEFF_PROBS_801
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_801_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_801_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_801_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_801_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_200, COEFF_PROBS_802
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_802_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_802_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_802_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_802_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_200, COEFF_PROBS_803
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_803_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_803_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_803_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_200_COEFF_PROBS_803_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_OFFSET	(0x0F18)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_201, COEFF_PROBS_804
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_804_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_804_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_804_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_804_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_201, COEFF_PROBS_805
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_805_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_805_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_805_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_805_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_201, COEFF_PROBS_806
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_806_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_806_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_806_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_806_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_201, COEFF_PROBS_807
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_807_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_807_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_807_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_201_COEFF_PROBS_807_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_OFFSET	(0x0F1C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_202, COEFF_PROBS_808
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_808_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_808_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_808_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_808_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_202, COEFF_PROBS_809
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_809_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_809_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_809_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_809_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_202, COEFF_PROBS_810
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_810_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_810_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_810_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_810_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_202, COEFF_PROBS_811
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_811_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_811_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_811_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_202_COEFF_PROBS_811_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_OFFSET	(0x0F20)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_203, COEFF_PROBS_812
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_812_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_812_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_812_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_812_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_203, COEFF_PROBS_813
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_813_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_813_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_813_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_813_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_203, COEFF_PROBS_814
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_814_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_814_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_814_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_814_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_203, COEFF_PROBS_815
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_815_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_815_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_815_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_203_COEFF_PROBS_815_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_OFFSET	(0x0F24)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_204, COEFF_PROBS_816
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_816_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_816_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_816_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_816_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_204, COEFF_PROBS_817
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_817_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_817_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_817_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_817_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_204, COEFF_PROBS_818
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_818_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_818_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_818_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_818_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_204, COEFF_PROBS_819
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_819_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_819_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_819_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_204_COEFF_PROBS_819_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_OFFSET	(0x0F28)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_205, COEFF_PROBS_820
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_820_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_820_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_820_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_820_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_205, COEFF_PROBS_821
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_821_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_821_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_821_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_821_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_205, COEFF_PROBS_822
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_822_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_822_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_822_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_822_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_205, COEFF_PROBS_823
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_823_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_823_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_823_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_205_COEFF_PROBS_823_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_OFFSET	(0x0F2C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_206, COEFF_PROBS_824
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_824_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_824_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_824_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_824_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_206, COEFF_PROBS_825
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_825_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_825_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_825_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_825_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_206, COEFF_PROBS_826
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_826_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_826_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_826_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_826_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_206, COEFF_PROBS_827
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_827_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_827_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_827_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_206_COEFF_PROBS_827_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_OFFSET	(0x0F30)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_207, COEFF_PROBS_828
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_828_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_828_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_828_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_828_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_207, COEFF_PROBS_829
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_829_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_829_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_829_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_829_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_207, COEFF_PROBS_830
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_830_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_830_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_830_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_830_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_207, COEFF_PROBS_831
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_831_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_831_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_831_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_207_COEFF_PROBS_831_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_OFFSET	(0x0F34)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_208, COEFF_PROBS_832
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_832_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_832_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_832_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_832_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_208, COEFF_PROBS_833
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_833_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_833_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_833_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_833_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_208, COEFF_PROBS_834
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_834_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_834_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_834_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_834_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_208, COEFF_PROBS_835
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_835_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_835_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_835_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_208_COEFF_PROBS_835_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_OFFSET	(0x0F38)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_209, COEFF_PROBS_836
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_836_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_836_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_836_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_836_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_209, COEFF_PROBS_837
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_837_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_837_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_837_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_837_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_209, COEFF_PROBS_838
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_838_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_838_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_838_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_838_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_209, COEFF_PROBS_839
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_839_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_839_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_839_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_209_COEFF_PROBS_839_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_OFFSET	(0x0F3C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_210, COEFF_PROBS_840
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_840_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_840_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_840_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_840_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_210, COEFF_PROBS_841
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_841_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_841_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_841_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_841_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_210, COEFF_PROBS_842
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_842_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_842_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_842_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_842_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_210, COEFF_PROBS_843
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_843_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_843_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_843_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_210_COEFF_PROBS_843_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_OFFSET	(0x0F40)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_211, COEFF_PROBS_844
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_844_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_844_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_844_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_844_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_211, COEFF_PROBS_845
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_845_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_845_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_845_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_845_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_211, COEFF_PROBS_846
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_846_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_846_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_846_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_846_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_211, COEFF_PROBS_847
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_847_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_847_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_847_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_211_COEFF_PROBS_847_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_OFFSET	(0x0F44)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_212, COEFF_PROBS_848
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_848_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_848_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_848_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_848_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_212, COEFF_PROBS_849
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_849_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_849_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_849_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_849_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_212, COEFF_PROBS_850
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_850_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_850_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_850_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_850_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_212, COEFF_PROBS_851
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_851_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_851_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_851_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_212_COEFF_PROBS_851_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_OFFSET	(0x0F48)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_213, COEFF_PROBS_852
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_852_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_852_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_852_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_852_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_213, COEFF_PROBS_853
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_853_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_853_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_853_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_853_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_213, COEFF_PROBS_854
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_854_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_854_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_854_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_854_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_213, COEFF_PROBS_855
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_855_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_855_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_855_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_213_COEFF_PROBS_855_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_OFFSET	(0x0F4C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_214, COEFF_PROBS_856
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_856_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_856_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_856_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_856_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_214, COEFF_PROBS_857
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_857_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_857_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_857_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_857_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_214, COEFF_PROBS_858
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_858_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_858_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_858_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_858_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_214, COEFF_PROBS_859
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_859_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_859_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_859_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_214_COEFF_PROBS_859_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_OFFSET	(0x0F50)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_215, COEFF_PROBS_860
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_860_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_860_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_860_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_860_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_215, COEFF_PROBS_861
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_861_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_861_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_861_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_861_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_215, COEFF_PROBS_862
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_862_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_862_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_862_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_862_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_215, COEFF_PROBS_863
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_863_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_863_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_863_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_215_COEFF_PROBS_863_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_OFFSET	(0x0F54)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_216, COEFF_PROBS_864
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_864_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_864_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_864_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_864_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_216, COEFF_PROBS_865
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_865_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_865_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_865_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_865_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_216, COEFF_PROBS_866
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_866_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_866_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_866_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_866_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_216, COEFF_PROBS_867
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_867_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_867_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_867_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_216_COEFF_PROBS_867_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_OFFSET	(0x0F58)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_217, COEFF_PROBS_868
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_868_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_868_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_868_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_868_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_217, COEFF_PROBS_869
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_869_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_869_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_869_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_869_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_217, COEFF_PROBS_870
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_870_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_870_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_870_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_870_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_217, COEFF_PROBS_871
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_871_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_871_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_871_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_217_COEFF_PROBS_871_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_OFFSET	(0x0F5C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_218, COEFF_PROBS_872
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_872_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_872_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_872_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_872_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_218, COEFF_PROBS_873
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_873_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_873_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_873_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_873_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_218, COEFF_PROBS_874
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_874_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_874_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_874_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_874_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_218, COEFF_PROBS_875
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_875_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_875_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_875_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_218_COEFF_PROBS_875_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_OFFSET	(0x0F60)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_219, COEFF_PROBS_876
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_876_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_876_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_876_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_876_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_219, COEFF_PROBS_877
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_877_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_877_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_877_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_877_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_219, COEFF_PROBS_878
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_878_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_878_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_878_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_878_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_219, COEFF_PROBS_879
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_879_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_879_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_879_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_219_COEFF_PROBS_879_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_OFFSET	(0x0F64)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_220, COEFF_PROBS_880
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_880_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_880_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_880_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_880_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_220, COEFF_PROBS_881
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_881_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_881_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_881_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_881_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_220, COEFF_PROBS_882
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_882_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_882_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_882_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_882_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_220, COEFF_PROBS_883
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_883_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_883_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_883_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_220_COEFF_PROBS_883_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_OFFSET	(0x0F68)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_221, COEFF_PROBS_884
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_884_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_884_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_884_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_884_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_221, COEFF_PROBS_885
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_885_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_885_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_885_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_885_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_221, COEFF_PROBS_886
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_886_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_886_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_886_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_886_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_221, COEFF_PROBS_887
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_887_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_887_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_887_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_221_COEFF_PROBS_887_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_OFFSET	(0x0F6C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_222, COEFF_PROBS_888
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_888_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_888_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_888_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_888_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_222, COEFF_PROBS_889
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_889_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_889_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_889_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_889_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_222, COEFF_PROBS_890
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_890_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_890_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_890_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_890_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_222, COEFF_PROBS_891
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_891_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_891_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_891_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_222_COEFF_PROBS_891_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_OFFSET	(0x0F70)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_223, COEFF_PROBS_892
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_892_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_892_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_892_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_892_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_223, COEFF_PROBS_893
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_893_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_893_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_893_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_893_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_223, COEFF_PROBS_894
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_894_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_894_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_894_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_894_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_223, COEFF_PROBS_895
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_895_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_895_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_895_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_223_COEFF_PROBS_895_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_OFFSET	(0x0F74)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_224, COEFF_PROBS_896
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_896_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_896_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_896_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_896_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_224, COEFF_PROBS_897
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_897_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_897_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_897_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_897_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_224, COEFF_PROBS_898
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_898_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_898_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_898_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_898_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_224, COEFF_PROBS_899
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_899_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_899_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_899_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_224_COEFF_PROBS_899_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_OFFSET	(0x0F78)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_225, COEFF_PROBS_900
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_900_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_900_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_900_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_900_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_225, COEFF_PROBS_901
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_901_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_901_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_901_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_901_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_225, COEFF_PROBS_902
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_902_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_902_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_902_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_902_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_225, COEFF_PROBS_903
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_903_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_903_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_903_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_225_COEFF_PROBS_903_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_OFFSET	(0x0F7C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_226, COEFF_PROBS_904
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_904_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_904_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_904_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_904_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_226, COEFF_PROBS_905
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_905_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_905_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_905_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_905_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_226, COEFF_PROBS_906
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_906_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_906_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_906_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_906_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_226, COEFF_PROBS_907
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_907_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_907_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_907_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_226_COEFF_PROBS_907_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_OFFSET	(0x0F80)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_227, COEFF_PROBS_908
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_908_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_908_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_908_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_908_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_227, COEFF_PROBS_909
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_909_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_909_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_909_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_909_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_227, COEFF_PROBS_910
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_910_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_910_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_910_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_910_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_227, COEFF_PROBS_911
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_911_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_911_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_911_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_227_COEFF_PROBS_911_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_OFFSET	(0x0F84)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_228, COEFF_PROBS_912
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_912_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_912_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_912_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_912_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_228, COEFF_PROBS_913
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_913_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_913_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_913_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_913_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_228, COEFF_PROBS_914
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_914_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_914_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_914_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_914_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_228, COEFF_PROBS_915
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_915_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_915_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_915_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_228_COEFF_PROBS_915_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_OFFSET	(0x0F88)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_229, COEFF_PROBS_916
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_916_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_916_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_916_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_916_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_229, COEFF_PROBS_917
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_917_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_917_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_917_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_917_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_229, COEFF_PROBS_918
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_918_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_918_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_918_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_918_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_229, COEFF_PROBS_919
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_919_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_919_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_919_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_229_COEFF_PROBS_919_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_OFFSET	(0x0F8C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_230, COEFF_PROBS_920
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_920_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_920_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_920_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_920_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_230, COEFF_PROBS_921
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_921_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_921_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_921_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_921_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_230, COEFF_PROBS_922
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_922_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_922_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_922_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_922_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_230, COEFF_PROBS_923
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_923_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_923_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_923_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_230_COEFF_PROBS_923_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_OFFSET	(0x0F90)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_231, COEFF_PROBS_924
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_924_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_924_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_924_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_924_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_231, COEFF_PROBS_925
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_925_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_925_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_925_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_925_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_231, COEFF_PROBS_926
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_926_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_926_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_926_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_926_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_231, COEFF_PROBS_927
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_927_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_927_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_927_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_231_COEFF_PROBS_927_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_OFFSET	(0x0F94)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_232, COEFF_PROBS_928
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_928_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_928_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_928_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_928_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_232, COEFF_PROBS_929
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_929_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_929_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_929_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_929_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_232, COEFF_PROBS_930
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_930_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_930_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_930_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_930_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_232, COEFF_PROBS_931
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_931_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_931_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_931_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_232_COEFF_PROBS_931_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_OFFSET	(0x0F98)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_233, COEFF_PROBS_932
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_932_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_932_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_932_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_932_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_233, COEFF_PROBS_933
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_933_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_933_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_933_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_933_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_233, COEFF_PROBS_934
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_934_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_934_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_934_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_934_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_233, COEFF_PROBS_935
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_935_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_935_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_935_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_233_COEFF_PROBS_935_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_OFFSET	(0x0F9C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_234, COEFF_PROBS_936
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_936_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_936_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_936_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_936_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_234, COEFF_PROBS_937
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_937_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_937_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_937_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_937_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_234, COEFF_PROBS_938
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_938_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_938_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_938_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_938_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_234, COEFF_PROBS_939
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_939_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_939_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_939_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_234_COEFF_PROBS_939_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_OFFSET	(0x0FA0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_235, COEFF_PROBS_940
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_940_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_940_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_940_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_940_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_235, COEFF_PROBS_941
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_941_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_941_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_941_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_941_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_235, COEFF_PROBS_942
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_942_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_942_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_942_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_942_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_235, COEFF_PROBS_943
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_943_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_943_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_943_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_235_COEFF_PROBS_943_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_OFFSET	(0x0FA4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_236, COEFF_PROBS_944
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_944_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_944_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_944_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_944_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_236, COEFF_PROBS_945
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_945_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_945_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_945_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_945_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_236, COEFF_PROBS_946
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_946_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_946_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_946_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_946_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_236, COEFF_PROBS_947
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_947_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_947_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_947_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_236_COEFF_PROBS_947_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_OFFSET	(0x0FA8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_237, COEFF_PROBS_948
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_948_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_948_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_948_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_948_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_237, COEFF_PROBS_949
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_949_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_949_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_949_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_949_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_237, COEFF_PROBS_950
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_950_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_950_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_950_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_950_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_237, COEFF_PROBS_951
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_951_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_951_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_951_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_237_COEFF_PROBS_951_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_OFFSET	(0x0FAC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_238, COEFF_PROBS_952
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_952_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_952_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_952_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_952_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_238, COEFF_PROBS_953
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_953_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_953_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_953_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_953_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_238, COEFF_PROBS_954
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_954_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_954_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_954_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_954_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_238, COEFF_PROBS_955
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_955_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_955_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_955_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_238_COEFF_PROBS_955_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_OFFSET	(0x0FB0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_239, COEFF_PROBS_956
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_956_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_956_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_956_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_956_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_239, COEFF_PROBS_957
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_957_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_957_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_957_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_957_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_239, COEFF_PROBS_958
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_958_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_958_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_958_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_958_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_239, COEFF_PROBS_959
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_959_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_959_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_959_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_239_COEFF_PROBS_959_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_OFFSET	(0x0FB4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_240, COEFF_PROBS_960
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_960_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_960_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_960_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_960_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_240, COEFF_PROBS_961
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_961_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_961_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_961_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_961_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_240, COEFF_PROBS_962
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_962_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_962_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_962_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_962_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_240, COEFF_PROBS_963
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_963_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_963_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_963_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_240_COEFF_PROBS_963_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_OFFSET	(0x0FB8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_241, COEFF_PROBS_964
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_964_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_964_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_964_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_964_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_241, COEFF_PROBS_965
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_965_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_965_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_965_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_965_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_241, COEFF_PROBS_966
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_966_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_966_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_966_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_966_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_241, COEFF_PROBS_967
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_967_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_967_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_967_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_241_COEFF_PROBS_967_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_OFFSET	(0x0FBC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_242, COEFF_PROBS_968
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_968_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_968_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_968_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_968_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_242, COEFF_PROBS_969
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_969_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_969_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_969_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_969_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_242, COEFF_PROBS_970
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_970_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_970_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_970_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_970_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_242, COEFF_PROBS_971
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_971_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_971_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_971_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_242_COEFF_PROBS_971_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_OFFSET	(0x0FC0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_243, COEFF_PROBS_972
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_972_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_972_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_972_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_972_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_243, COEFF_PROBS_973
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_973_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_973_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_973_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_973_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_243, COEFF_PROBS_974
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_974_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_974_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_974_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_974_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_243, COEFF_PROBS_975
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_975_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_975_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_975_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_243_COEFF_PROBS_975_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_OFFSET	(0x0FC4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_244, COEFF_PROBS_976
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_976_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_976_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_976_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_976_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_244, COEFF_PROBS_977
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_977_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_977_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_977_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_977_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_244, COEFF_PROBS_978
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_978_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_978_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_978_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_978_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_244, COEFF_PROBS_979
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_979_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_979_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_979_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_244_COEFF_PROBS_979_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_OFFSET	(0x0FC8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_245, COEFF_PROBS_980
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_980_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_980_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_980_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_980_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_245, COEFF_PROBS_981
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_981_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_981_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_981_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_981_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_245, COEFF_PROBS_982
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_982_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_982_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_982_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_982_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_245, COEFF_PROBS_983
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_983_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_983_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_983_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_245_COEFF_PROBS_983_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_OFFSET	(0x0FCC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_246, COEFF_PROBS_984
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_984_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_984_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_984_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_984_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_246, COEFF_PROBS_985
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_985_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_985_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_985_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_985_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_246, COEFF_PROBS_986
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_986_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_986_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_986_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_986_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_246, COEFF_PROBS_987
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_987_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_987_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_987_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_246_COEFF_PROBS_987_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_OFFSET	(0x0FD0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_247, COEFF_PROBS_988
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_988_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_988_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_988_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_988_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_247, COEFF_PROBS_989
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_989_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_989_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_989_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_989_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_247, COEFF_PROBS_990
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_990_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_990_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_990_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_990_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_247, COEFF_PROBS_991
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_991_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_991_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_991_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_247_COEFF_PROBS_991_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_OFFSET	(0x0FD4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_248, COEFF_PROBS_992
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_992_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_992_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_992_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_992_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_248, COEFF_PROBS_993
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_993_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_993_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_993_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_993_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_248, COEFF_PROBS_994
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_994_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_994_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_994_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_994_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_248, COEFF_PROBS_995
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_995_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_995_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_995_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_248_COEFF_PROBS_995_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_OFFSET	(0x0FD8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_249, COEFF_PROBS_996
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_996_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_996_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_996_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_996_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_249, COEFF_PROBS_997
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_997_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_997_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_997_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_997_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_249, COEFF_PROBS_998
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_998_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_998_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_998_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_998_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_249, COEFF_PROBS_999
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_999_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_999_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_999_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_249_COEFF_PROBS_999_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_OFFSET	(0x0FDC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_250, COEFF_PROBS_1000
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1000_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1000_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1000_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1000_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_250, COEFF_PROBS_1001
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1001_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1001_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1001_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1001_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_250, COEFF_PROBS_1002
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1002_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1002_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1002_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1002_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_250, COEFF_PROBS_1003
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1003_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1003_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1003_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_250_COEFF_PROBS_1003_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_OFFSET	(0x0FE0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_251, COEFF_PROBS_1004
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1004_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1004_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1004_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1004_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_251, COEFF_PROBS_1005
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1005_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1005_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1005_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1005_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_251, COEFF_PROBS_1006
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1006_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1006_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1006_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1006_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_251, COEFF_PROBS_1007
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1007_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1007_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1007_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_251_COEFF_PROBS_1007_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_OFFSET	(0x0FE4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_252, COEFF_PROBS_1008
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1008_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1008_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1008_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1008_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_252, COEFF_PROBS_1009
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1009_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1009_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1009_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1009_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_252, COEFF_PROBS_1010
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1010_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1010_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1010_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1010_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_252, COEFF_PROBS_1011
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1011_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1011_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1011_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_252_COEFF_PROBS_1011_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_OFFSET	(0x0FE8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_253, COEFF_PROBS_1012
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1012_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1012_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1012_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1012_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_253, COEFF_PROBS_1013
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1013_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1013_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1013_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1013_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_253, COEFF_PROBS_1014
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1014_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1014_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1014_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1014_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_253, COEFF_PROBS_1015
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1015_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1015_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1015_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_253_COEFF_PROBS_1015_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_OFFSET	(0x0FEC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_254, COEFF_PROBS_1016
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1016_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1016_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1016_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1016_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_254, COEFF_PROBS_1017
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1017_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1017_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1017_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1017_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_254, COEFF_PROBS_1018
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1018_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1018_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1018_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1018_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_254, COEFF_PROBS_1019
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1019_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1019_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1019_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_254_COEFF_PROBS_1019_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_OFFSET	(0x0FF0)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_255, COEFF_PROBS_1020
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1020_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1020_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1020_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1020_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_255, COEFF_PROBS_1021
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1021_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1021_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1021_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1021_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_255, COEFF_PROBS_1022
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1022_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1022_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1022_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1022_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_255, COEFF_PROBS_1023
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1023_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1023_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1023_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_255_COEFF_PROBS_1023_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_OFFSET	(0x0FF4)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_256, COEFF_PROBS_1024
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1024_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1024_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1024_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1024_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_256, COEFF_PROBS_1025
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1025_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1025_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1025_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1025_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_256, COEFF_PROBS_1026
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1026_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1026_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1026_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1026_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_256, COEFF_PROBS_1027
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1027_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1027_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1027_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_256_COEFF_PROBS_1027_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_OFFSET	(0x0FF8)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_257, COEFF_PROBS_1028
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1028_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1028_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1028_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1028_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_257, COEFF_PROBS_1029
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1029_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1029_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1029_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1029_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_257, COEFF_PROBS_1030
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1030_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1030_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1030_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1030_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_257, COEFF_PROBS_1031
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1031_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1031_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1031_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_257_COEFF_PROBS_1031_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_OFFSET	(0x0FFC)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_258, COEFF_PROBS_1032
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1032_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1032_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1032_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1032_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_258, COEFF_PROBS_1033
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1033_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1033_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1033_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1033_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_258, COEFF_PROBS_1034
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1034_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1034_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1034_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1034_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_258, COEFF_PROBS_1035
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1035_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1035_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1035_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_258_COEFF_PROBS_1035_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_OFFSET	(0x1000)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_259, COEFF_PROBS_1036
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1036_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1036_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1036_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1036_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_259, COEFF_PROBS_1037
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1037_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1037_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1037_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1037_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_259, COEFF_PROBS_1038
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1038_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1038_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1038_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1038_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_259, COEFF_PROBS_1039
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1039_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1039_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1039_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_259_COEFF_PROBS_1039_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_OFFSET	(0x1004)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_260, COEFF_PROBS_1040
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1040_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1040_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1040_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1040_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_260, COEFF_PROBS_1041
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1041_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1041_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1041_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1041_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_260, COEFF_PROBS_1042
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1042_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1042_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1042_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1042_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_260, COEFF_PROBS_1043
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1043_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1043_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1043_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_260_COEFF_PROBS_1043_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_OFFSET	(0x1008)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_261, COEFF_PROBS_1044
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1044_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1044_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1044_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1044_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_261, COEFF_PROBS_1045
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1045_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1045_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1045_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1045_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_261, COEFF_PROBS_1046
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1046_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1046_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1046_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1046_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_261, COEFF_PROBS_1047
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1047_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1047_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1047_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_261_COEFF_PROBS_1047_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_OFFSET	(0x100C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_262, COEFF_PROBS_1048
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1048_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1048_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1048_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1048_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_262, COEFF_PROBS_1049
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1049_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1049_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1049_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1049_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_262, COEFF_PROBS_1050
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1050_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1050_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1050_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1050_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_262, COEFF_PROBS_1051
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1051_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1051_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1051_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_262_COEFF_PROBS_1051_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_OFFSET	(0x1010)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_263, COEFF_PROBS_1052
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1052_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1052_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1052_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1052_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_263, COEFF_PROBS_1053
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1053_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1053_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1053_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1053_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_263, COEFF_PROBS_1054
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1054_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1054_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1054_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1054_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_PROBS_REG_263, COEFF_PROBS_1055
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1055_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1055_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1055_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_PROBS_REG_263_COEFF_PROBS_1055_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_OFFSET	(0x1014)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT1_PROBS_REG_00, COEFF_CAT1_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT1_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT1_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT1_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT1_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT1_PROBS_REG_00, COEFF_CAT2_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_00_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_00_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT1_PROBS_REG_00, COEFF_CAT2_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_01_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_01_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT1_PROBS_REG_00_COEFF_CAT2_PROBS_01_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_OFFSET	(0x1018)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT3_PROBS_REG_00, COEFF_CAT3_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT3_PROBS_REG_00, COEFF_CAT3_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT3_PROBS_REG_00, COEFF_CAT3_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT3_PROBS_REG_00_COEFF_CAT3_PROBS_02_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_OFFSET	(0x101C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT4_PROBS_REG_00, COEFF_CAT4_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT4_PROBS_REG_00, COEFF_CAT4_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT4_PROBS_REG_00, COEFF_CAT4_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT4_PROBS_REG_00, COEFF_CAT4_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_03_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT4_PROBS_REG_00_COEFF_CAT4_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_OFFSET	(0x1020)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT5_PROBS_REG_00, COEFF_CAT5_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT5_PROBS_REG_00, COEFF_CAT5_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT5_PROBS_REG_00, COEFF_CAT5_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT5_PROBS_REG_00, COEFF_CAT5_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_03_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_00_COEFF_CAT5_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_01_OFFSET	(0x1024)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT5_PROBS_REG_01, COEFF_CAT5_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_01_COEFF_CAT5_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_01_COEFF_CAT5_PROBS_04_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_01_COEFF_CAT5_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT5_PROBS_REG_01_COEFF_CAT5_PROBS_04_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_OFFSET	(0x1028)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_00, COEFF_CAT6_PROBS_00
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_00_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_00_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_00_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_00_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_00, COEFF_CAT6_PROBS_01
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_01_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_01_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_01_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_01_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_00, COEFF_CAT6_PROBS_02
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_02_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_02_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_02_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_02_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_00, COEFF_CAT6_PROBS_03
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_03_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_03_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_03_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_00_COEFF_CAT6_PROBS_03_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_OFFSET	(0x102C)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_01, COEFF_CAT6_PROBS_04
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_04_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_04_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_04_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_04_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_01, COEFF_CAT6_PROBS_05
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_05_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_05_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_05_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_05_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_01, COEFF_CAT6_PROBS_06
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_06_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_06_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_06_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_06_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_01, COEFF_CAT6_PROBS_07
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_07_MASK		(0xFF000000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_07_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_07_SHIFT		(24)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_01_COEFF_CAT6_PROBS_07_SIGNED_FIELD	IMG_FALSE

#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_OFFSET	(0x1030)

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_02, COEFF_CAT6_PROBS_08
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_08_MASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_08_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_08_SHIFT		(0)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_08_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_02, COEFF_CAT6_PROBS_09
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_09_MASK		(0x0000FF00)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_09_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_09_SHIFT		(8)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_09_SIGNED_FIELD	IMG_FALSE

// MSVDX_VEC_LINE_STORE_RAM, COEFF_CAT6_PROBS_REG_02, COEFF_CAT6_PROBS_10
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_10_MASK		(0x00FF0000)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_10_LSBMASK		(0x000000FF)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_10_SHIFT		(16)
#define MSVDX_VEC_LINE_STORE_RAM_COEFF_CAT6_PROBS_REG_02_COEFF_CAT6_PROBS_10_SIGNED_FIELD	IMG_FALSE



#ifdef __cplusplus
}
#endif

#endif /* __MSVDX_VEC_VP8_LINE_STORE_MEM_IO2_H__ */