1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 /** 37 * DOC: uevents generated by i915 on it's device node 38 * 39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40 * event from the gpu l3 cache. Additional information supplied is ROW, 41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42 * track of these events and if a specific cache-line seems to have a 43 * persistent error remap it with the l3 remapping tool supplied in 44 * intel-gpu-tools. The value supplied with the event is always 1. 45 * 46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47 * hangcheck. The error detection event is a good indicator of when things 48 * began to go badly. The value supplied with the event is a 1 upon error 49 * detection, and a 0 upon reset completion, signifying no more error 50 * exists. NOTE: Disabling hangcheck or reset via module parameter will 51 * cause the related events to not be seen. 52 * 53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54 * the GPU. The value supplied with the event is always 1. NOTE: Disable 55 * reset via module parameter will cause this event to not be seen. 56 */ 57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58 #define I915_ERROR_UEVENT "ERROR" 59 #define I915_RESET_UEVENT "RESET" 60 61 /* Each region is a minimum of 16k, and there are at most 255 of them. 62 */ 63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64 * of chars for next/prev indices */ 65 #define I915_LOG_MIN_TEX_REGION_SIZE 14 66 67 typedef struct _drm_i915_init { 68 enum { 69 I915_INIT_DMA = 0x01, 70 I915_CLEANUP_DMA = 0x02, 71 I915_RESUME_DMA = 0x03 72 } func; 73 unsigned int mmio_offset; 74 int sarea_priv_offset; 75 unsigned int ring_start; 76 unsigned int ring_end; 77 unsigned int ring_size; 78 unsigned int front_offset; 79 unsigned int back_offset; 80 unsigned int depth_offset; 81 unsigned int w; 82 unsigned int h; 83 unsigned int pitch; 84 unsigned int pitch_bits; 85 unsigned int back_pitch; 86 unsigned int depth_pitch; 87 unsigned int cpp; 88 unsigned int chipset; 89 } drm_i915_init_t; 90 91 typedef struct _drm_i915_sarea { 92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93 int last_upload; /* last time texture was uploaded */ 94 int last_enqueue; /* last time a buffer was enqueued */ 95 int last_dispatch; /* age of the most recently dispatched buffer */ 96 int ctxOwner; /* last context to upload state */ 97 int texAge; 98 int pf_enabled; /* is pageflipping allowed? */ 99 int pf_active; 100 int pf_current_page; /* which buffer is being displayed? */ 101 int perf_boxes; /* performance boxes to be displayed */ 102 int width, height; /* screen size in pixels */ 103 104 drm_handle_t front_handle; 105 int front_offset; 106 int front_size; 107 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 112 drm_handle_t depth_handle; 113 int depth_offset; 114 int depth_size; 115 116 drm_handle_t tex_handle; 117 int tex_offset; 118 int tex_size; 119 int log_tex_granularity; 120 int pitch; 121 int rotation; /* 0, 90, 180 or 270 */ 122 int rotated_offset; 123 int rotated_size; 124 int rotated_pitch; 125 int virtualX, virtualY; 126 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 133 int pipeA_x; 134 int pipeA_y; 135 int pipeA_w; 136 int pipeA_h; 137 int pipeB_x; 138 int pipeB_y; 139 int pipeB_w; 140 int pipeB_h; 141 142 /* fill out some space for old userspace triple buffer */ 143 drm_handle_t unused_handle; 144 __u32 unused1, unused2, unused3; 145 146 /* buffer object handles for static buffers. May change 147 * over the lifetime of the client. 148 */ 149 __u32 front_bo_handle; 150 __u32 back_bo_handle; 151 __u32 unused_bo_handle; 152 __u32 depth_bo_handle; 153 154 } drm_i915_sarea_t; 155 156 /* due to userspace building against these headers we need some compat here */ 157 #define planeA_x pipeA_x 158 #define planeA_y pipeA_y 159 #define planeA_w pipeA_w 160 #define planeA_h pipeA_h 161 #define planeB_x pipeB_x 162 #define planeB_y pipeB_y 163 #define planeB_w pipeB_w 164 #define planeB_h pipeB_h 165 166 /* Flags for perf_boxes 167 */ 168 #define I915_BOX_RING_EMPTY 0x1 169 #define I915_BOX_FLIP 0x2 170 #define I915_BOX_WAIT 0x4 171 #define I915_BOX_TEXTURE_LOAD 0x8 172 #define I915_BOX_LOST_CONTEXT 0x10 173 174 /* 175 * i915 specific ioctls. 176 * 177 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 178 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 179 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 180 */ 181 #define DRM_I915_INIT 0x00 182 #define DRM_I915_FLUSH 0x01 183 #define DRM_I915_FLIP 0x02 184 #define DRM_I915_BATCHBUFFER 0x03 185 #define DRM_I915_IRQ_EMIT 0x04 186 #define DRM_I915_IRQ_WAIT 0x05 187 #define DRM_I915_GETPARAM 0x06 188 #define DRM_I915_SETPARAM 0x07 189 #define DRM_I915_ALLOC 0x08 190 #define DRM_I915_FREE 0x09 191 #define DRM_I915_INIT_HEAP 0x0a 192 #define DRM_I915_CMDBUFFER 0x0b 193 #define DRM_I915_DESTROY_HEAP 0x0c 194 #define DRM_I915_SET_VBLANK_PIPE 0x0d 195 #define DRM_I915_GET_VBLANK_PIPE 0x0e 196 #define DRM_I915_VBLANK_SWAP 0x0f 197 #define DRM_I915_HWS_ADDR 0x11 198 #define DRM_I915_GEM_INIT 0x13 199 #define DRM_I915_GEM_EXECBUFFER 0x14 200 #define DRM_I915_GEM_PIN 0x15 201 #define DRM_I915_GEM_UNPIN 0x16 202 #define DRM_I915_GEM_BUSY 0x17 203 #define DRM_I915_GEM_THROTTLE 0x18 204 #define DRM_I915_GEM_ENTERVT 0x19 205 #define DRM_I915_GEM_LEAVEVT 0x1a 206 #define DRM_I915_GEM_CREATE 0x1b 207 #define DRM_I915_GEM_PREAD 0x1c 208 #define DRM_I915_GEM_PWRITE 0x1d 209 #define DRM_I915_GEM_MMAP 0x1e 210 #define DRM_I915_GEM_SET_DOMAIN 0x1f 211 #define DRM_I915_GEM_SW_FINISH 0x20 212 #define DRM_I915_GEM_SET_TILING 0x21 213 #define DRM_I915_GEM_GET_TILING 0x22 214 #define DRM_I915_GEM_GET_APERTURE 0x23 215 #define DRM_I915_GEM_MMAP_GTT 0x24 216 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 217 #define DRM_I915_GEM_MADVISE 0x26 218 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 219 #define DRM_I915_OVERLAY_ATTRS 0x28 220 #define DRM_I915_GEM_EXECBUFFER2 0x29 221 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 222 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 223 #define DRM_I915_GEM_WAIT 0x2c 224 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 225 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 226 #define DRM_I915_GEM_SET_CACHING 0x2f 227 #define DRM_I915_GEM_GET_CACHING 0x30 228 #define DRM_I915_REG_READ 0x31 229 #define DRM_I915_GET_RESET_STATS 0x32 230 #define DRM_I915_GEM_USERPTR 0x33 231 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 232 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 233 234 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 235 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 236 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 237 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 238 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 239 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 240 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 241 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 242 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 243 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 244 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 245 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 246 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 247 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 248 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 249 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 250 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 251 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 252 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 253 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 254 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 255 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 256 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 257 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 258 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 259 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 260 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 261 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 262 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 263 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 264 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 265 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 266 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 267 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 268 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 269 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 270 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 271 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 272 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 273 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 274 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 275 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 276 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 277 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 278 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 279 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 280 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 281 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 282 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 283 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 284 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 285 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 286 287 /* Allow drivers to submit batchbuffers directly to hardware, relying 288 * on the security mechanisms provided by hardware. 289 */ 290 typedef struct drm_i915_batchbuffer { 291 int start; /* agp offset */ 292 int used; /* nr bytes in use */ 293 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 294 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 295 int num_cliprects; /* mulitpass with multiple cliprects? */ 296 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 297 } drm_i915_batchbuffer_t; 298 299 /* As above, but pass a pointer to userspace buffer which can be 300 * validated by the kernel prior to sending to hardware. 301 */ 302 typedef struct _drm_i915_cmdbuffer { 303 char *buf; /* pointer to userspace command buffer */ 304 int sz; /* nr bytes in buf */ 305 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 306 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 307 int num_cliprects; /* mulitpass with multiple cliprects? */ 308 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 309 } drm_i915_cmdbuffer_t; 310 311 /* Userspace can request & wait on irq's: 312 */ 313 typedef struct drm_i915_irq_emit { 314 int *irq_seq; 315 } drm_i915_irq_emit_t; 316 317 typedef struct drm_i915_irq_wait { 318 int irq_seq; 319 } drm_i915_irq_wait_t; 320 321 /* Ioctl to query kernel params: 322 */ 323 #define I915_PARAM_IRQ_ACTIVE 1 324 #define I915_PARAM_ALLOW_BATCHBUFFER 2 325 #define I915_PARAM_LAST_DISPATCH 3 326 #define I915_PARAM_CHIPSET_ID 4 327 #define I915_PARAM_HAS_GEM 5 328 #define I915_PARAM_NUM_FENCES_AVAIL 6 329 #define I915_PARAM_HAS_OVERLAY 7 330 #define I915_PARAM_HAS_PAGEFLIPPING 8 331 #define I915_PARAM_HAS_EXECBUF2 9 332 #define I915_PARAM_HAS_BSD 10 333 #define I915_PARAM_HAS_BLT 11 334 #define I915_PARAM_HAS_RELAXED_FENCING 12 335 #define I915_PARAM_HAS_COHERENT_RINGS 13 336 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 337 #define I915_PARAM_HAS_RELAXED_DELTA 15 338 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 339 #define I915_PARAM_HAS_LLC 17 340 #define I915_PARAM_HAS_ALIASING_PPGTT 18 341 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 342 #define I915_PARAM_HAS_SEMAPHORES 20 343 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 344 #define I915_PARAM_HAS_VEBOX 22 345 #define I915_PARAM_HAS_SECURE_BATCHES 23 346 #define I915_PARAM_HAS_PINNED_BATCHES 24 347 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 348 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 349 #define I915_PARAM_HAS_WT 27 350 #define I915_PARAM_CMD_PARSER_VERSION 28 351 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 352 #define I915_PARAM_MMAP_VERSION 30 353 #define I915_PARAM_HAS_BSD2 31 354 #define I915_PARAM_REVISION 32 355 #define I915_PARAM_SUBSLICE_TOTAL 33 356 #define I915_PARAM_EU_TOTAL 34 357 #define I915_PARAM_HAS_GPU_RESET 35 358 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 359 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 360 361 typedef struct drm_i915_getparam { 362 __s32 param; 363 /* 364 * WARNING: Using pointers instead of fixed-size u64 means we need to write 365 * compat32 code. Don't repeat this mistake. 366 */ 367 int *value; 368 } drm_i915_getparam_t; 369 370 /* Ioctl to set kernel params: 371 */ 372 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 373 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 374 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 375 #define I915_SETPARAM_NUM_USED_FENCES 4 376 377 typedef struct drm_i915_setparam { 378 int param; 379 int value; 380 } drm_i915_setparam_t; 381 382 /* A memory manager for regions of shared memory: 383 */ 384 #define I915_MEM_REGION_AGP 1 385 386 typedef struct drm_i915_mem_alloc { 387 int region; 388 int alignment; 389 int size; 390 int *region_offset; /* offset from start of fb or agp */ 391 } drm_i915_mem_alloc_t; 392 393 typedef struct drm_i915_mem_free { 394 int region; 395 int region_offset; 396 } drm_i915_mem_free_t; 397 398 typedef struct drm_i915_mem_init_heap { 399 int region; 400 int size; 401 int start; 402 } drm_i915_mem_init_heap_t; 403 404 /* Allow memory manager to be torn down and re-initialized (eg on 405 * rotate): 406 */ 407 typedef struct drm_i915_mem_destroy_heap { 408 int region; 409 } drm_i915_mem_destroy_heap_t; 410 411 /* Allow X server to configure which pipes to monitor for vblank signals 412 */ 413 #define DRM_I915_VBLANK_PIPE_A 1 414 #define DRM_I915_VBLANK_PIPE_B 2 415 416 typedef struct drm_i915_vblank_pipe { 417 int pipe; 418 } drm_i915_vblank_pipe_t; 419 420 /* Schedule buffer swap at given vertical blank: 421 */ 422 typedef struct drm_i915_vblank_swap { 423 drm_drawable_t drawable; 424 enum drm_vblank_seq_type seqtype; 425 unsigned int sequence; 426 } drm_i915_vblank_swap_t; 427 428 typedef struct drm_i915_hws_addr { 429 __u64 addr; 430 } drm_i915_hws_addr_t; 431 432 struct drm_i915_gem_init { 433 /** 434 * Beginning offset in the GTT to be managed by the DRM memory 435 * manager. 436 */ 437 __u64 gtt_start; 438 /** 439 * Ending offset in the GTT to be managed by the DRM memory 440 * manager. 441 */ 442 __u64 gtt_end; 443 }; 444 445 struct drm_i915_gem_create { 446 /** 447 * Requested size for the object. 448 * 449 * The (page-aligned) allocated size for the object will be returned. 450 */ 451 __u64 size; 452 /** 453 * Returned handle for the object. 454 * 455 * Object handles are nonzero. 456 */ 457 __u32 handle; 458 __u32 pad; 459 }; 460 461 struct drm_i915_gem_pread { 462 /** Handle for the object being read. */ 463 __u32 handle; 464 __u32 pad; 465 /** Offset into the object to read from */ 466 __u64 offset; 467 /** Length of data to read */ 468 __u64 size; 469 /** 470 * Pointer to write the data into. 471 * 472 * This is a fixed-size type for 32/64 compatibility. 473 */ 474 __u64 data_ptr; 475 }; 476 477 struct drm_i915_gem_pwrite { 478 /** Handle for the object being written to. */ 479 __u32 handle; 480 __u32 pad; 481 /** Offset into the object to write to */ 482 __u64 offset; 483 /** Length of data to write */ 484 __u64 size; 485 /** 486 * Pointer to read the data from. 487 * 488 * This is a fixed-size type for 32/64 compatibility. 489 */ 490 __u64 data_ptr; 491 }; 492 493 struct drm_i915_gem_mmap { 494 /** Handle for the object being mapped. */ 495 __u32 handle; 496 __u32 pad; 497 /** Offset in the object to map. */ 498 __u64 offset; 499 /** 500 * Length of data to map. 501 * 502 * The value will be page-aligned. 503 */ 504 __u64 size; 505 /** 506 * Returned pointer the data was mapped at. 507 * 508 * This is a fixed-size type for 32/64 compatibility. 509 */ 510 __u64 addr_ptr; 511 512 /** 513 * Flags for extended behaviour. 514 * 515 * Added in version 2. 516 */ 517 __u64 flags; 518 #define I915_MMAP_WC 0x1 519 }; 520 521 struct drm_i915_gem_mmap_gtt { 522 /** Handle for the object being mapped. */ 523 __u32 handle; 524 __u32 pad; 525 /** 526 * Fake offset to use for subsequent mmap call 527 * 528 * This is a fixed-size type for 32/64 compatibility. 529 */ 530 __u64 offset; 531 }; 532 533 struct drm_i915_gem_set_domain { 534 /** Handle for the object */ 535 __u32 handle; 536 537 /** New read domains */ 538 __u32 read_domains; 539 540 /** New write domain */ 541 __u32 write_domain; 542 }; 543 544 struct drm_i915_gem_sw_finish { 545 /** Handle for the object */ 546 __u32 handle; 547 }; 548 549 struct drm_i915_gem_relocation_entry { 550 /** 551 * Handle of the buffer being pointed to by this relocation entry. 552 * 553 * It's appealing to make this be an index into the mm_validate_entry 554 * list to refer to the buffer, but this allows the driver to create 555 * a relocation list for state buffers and not re-write it per 556 * exec using the buffer. 557 */ 558 __u32 target_handle; 559 560 /** 561 * Value to be added to the offset of the target buffer to make up 562 * the relocation entry. 563 */ 564 __u32 delta; 565 566 /** Offset in the buffer the relocation entry will be written into */ 567 __u64 offset; 568 569 /** 570 * Offset value of the target buffer that the relocation entry was last 571 * written as. 572 * 573 * If the buffer has the same offset as last time, we can skip syncing 574 * and writing the relocation. This value is written back out by 575 * the execbuffer ioctl when the relocation is written. 576 */ 577 __u64 presumed_offset; 578 579 /** 580 * Target memory domains read by this operation. 581 */ 582 __u32 read_domains; 583 584 /** 585 * Target memory domains written by this operation. 586 * 587 * Note that only one domain may be written by the whole 588 * execbuffer operation, so that where there are conflicts, 589 * the application will get -EINVAL back. 590 */ 591 __u32 write_domain; 592 }; 593 594 /** @{ 595 * Intel memory domains 596 * 597 * Most of these just align with the various caches in 598 * the system and are used to flush and invalidate as 599 * objects end up cached in different domains. 600 */ 601 /** CPU cache */ 602 #define I915_GEM_DOMAIN_CPU 0x00000001 603 /** Render cache, used by 2D and 3D drawing */ 604 #define I915_GEM_DOMAIN_RENDER 0x00000002 605 /** Sampler cache, used by texture engine */ 606 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 607 /** Command queue, used to load batch buffers */ 608 #define I915_GEM_DOMAIN_COMMAND 0x00000008 609 /** Instruction cache, used by shader programs */ 610 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 611 /** Vertex address cache */ 612 #define I915_GEM_DOMAIN_VERTEX 0x00000020 613 /** GTT domain - aperture and scanout */ 614 #define I915_GEM_DOMAIN_GTT 0x00000040 615 /** @} */ 616 617 struct drm_i915_gem_exec_object { 618 /** 619 * User's handle for a buffer to be bound into the GTT for this 620 * operation. 621 */ 622 __u32 handle; 623 624 /** Number of relocations to be performed on this buffer */ 625 __u32 relocation_count; 626 /** 627 * Pointer to array of struct drm_i915_gem_relocation_entry containing 628 * the relocations to be performed in this buffer. 629 */ 630 __u64 relocs_ptr; 631 632 /** Required alignment in graphics aperture */ 633 __u64 alignment; 634 635 /** 636 * Returned value of the updated offset of the object, for future 637 * presumed_offset writes. 638 */ 639 __u64 offset; 640 }; 641 642 struct drm_i915_gem_execbuffer { 643 /** 644 * List of buffers to be validated with their relocations to be 645 * performend on them. 646 * 647 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 648 * 649 * These buffers must be listed in an order such that all relocations 650 * a buffer is performing refer to buffers that have already appeared 651 * in the validate list. 652 */ 653 __u64 buffers_ptr; 654 __u32 buffer_count; 655 656 /** Offset in the batchbuffer to start execution from. */ 657 __u32 batch_start_offset; 658 /** Bytes used in batchbuffer from batch_start_offset */ 659 __u32 batch_len; 660 __u32 DR1; 661 __u32 DR4; 662 __u32 num_cliprects; 663 /** This is a struct drm_clip_rect *cliprects */ 664 __u64 cliprects_ptr; 665 }; 666 667 struct drm_i915_gem_exec_object2 { 668 /** 669 * User's handle for a buffer to be bound into the GTT for this 670 * operation. 671 */ 672 __u32 handle; 673 674 /** Number of relocations to be performed on this buffer */ 675 __u32 relocation_count; 676 /** 677 * Pointer to array of struct drm_i915_gem_relocation_entry containing 678 * the relocations to be performed in this buffer. 679 */ 680 __u64 relocs_ptr; 681 682 /** Required alignment in graphics aperture */ 683 __u64 alignment; 684 685 /** 686 * When the EXEC_OBJECT_PINNED flag is specified this is populated by 687 * the user with the GTT offset at which this object will be pinned. 688 * When the I915_EXEC_NO_RELOC flag is specified this must contain the 689 * presumed_offset of the object. 690 * During execbuffer2 the kernel populates it with the value of the 691 * current GTT offset of the object, for future presumed_offset writes. 692 */ 693 __u64 offset; 694 695 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 696 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 697 #define EXEC_OBJECT_WRITE (1<<2) 698 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 699 #define EXEC_OBJECT_PINNED (1<<4) 700 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) 701 __u64 flags; 702 703 __u64 rsvd1; 704 __u64 rsvd2; 705 }; 706 707 struct drm_i915_gem_execbuffer2 { 708 /** 709 * List of gem_exec_object2 structs 710 */ 711 __u64 buffers_ptr; 712 __u32 buffer_count; 713 714 /** Offset in the batchbuffer to start execution from. */ 715 __u32 batch_start_offset; 716 /** Bytes used in batchbuffer from batch_start_offset */ 717 __u32 batch_len; 718 __u32 DR1; 719 __u32 DR4; 720 __u32 num_cliprects; 721 /** This is a struct drm_clip_rect *cliprects */ 722 __u64 cliprects_ptr; 723 #define I915_EXEC_RING_MASK (7<<0) 724 #define I915_EXEC_DEFAULT (0<<0) 725 #define I915_EXEC_RENDER (1<<0) 726 #define I915_EXEC_BSD (2<<0) 727 #define I915_EXEC_BLT (3<<0) 728 #define I915_EXEC_VEBOX (4<<0) 729 730 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 731 * Gen6+ only supports relative addressing to dynamic state (default) and 732 * absolute addressing. 733 * 734 * These flags are ignored for the BSD and BLT rings. 735 */ 736 #define I915_EXEC_CONSTANTS_MASK (3<<6) 737 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 738 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 739 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 740 __u64 flags; 741 __u64 rsvd1; /* now used for context info */ 742 __u64 rsvd2; 743 }; 744 745 /** Resets the SO write offset registers for transform feedback on gen7. */ 746 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 747 748 /** Request a privileged ("secure") batch buffer. Note only available for 749 * DRM_ROOT_ONLY | DRM_MASTER processes. 750 */ 751 #define I915_EXEC_SECURE (1<<9) 752 753 /** Inform the kernel that the batch is and will always be pinned. This 754 * negates the requirement for a workaround to be performed to avoid 755 * an incoherent CS (such as can be found on 830/845). If this flag is 756 * not passed, the kernel will endeavour to make sure the batch is 757 * coherent with the CS before execution. If this flag is passed, 758 * userspace assumes the responsibility for ensuring the same. 759 */ 760 #define I915_EXEC_IS_PINNED (1<<10) 761 762 /** Provide a hint to the kernel that the command stream and auxiliary 763 * state buffers already holds the correct presumed addresses and so the 764 * relocation process may be skipped if no buffers need to be moved in 765 * preparation for the execbuffer. 766 */ 767 #define I915_EXEC_NO_RELOC (1<<11) 768 769 /** Use the reloc.handle as an index into the exec object array rather 770 * than as the per-file handle. 771 */ 772 #define I915_EXEC_HANDLE_LUT (1<<12) 773 774 /** Used for switching BSD rings on the platforms with two BSD rings */ 775 #define I915_EXEC_BSD_MASK (3<<13) 776 #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ 777 #define I915_EXEC_BSD_RING1 (1<<13) 778 #define I915_EXEC_BSD_RING2 (2<<13) 779 780 /** Tell the kernel that the batchbuffer is processed by 781 * the resource streamer. 782 */ 783 #define I915_EXEC_RESOURCE_STREAMER (1<<15) 784 785 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) 786 787 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 788 #define i915_execbuffer2_set_context_id(eb2, context) \ 789 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 790 #define i915_execbuffer2_get_context_id(eb2) \ 791 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 792 793 struct drm_i915_gem_pin { 794 /** Handle of the buffer to be pinned. */ 795 __u32 handle; 796 __u32 pad; 797 798 /** alignment required within the aperture */ 799 __u64 alignment; 800 801 /** Returned GTT offset of the buffer. */ 802 __u64 offset; 803 }; 804 805 struct drm_i915_gem_unpin { 806 /** Handle of the buffer to be unpinned. */ 807 __u32 handle; 808 __u32 pad; 809 }; 810 811 struct drm_i915_gem_busy { 812 /** Handle of the buffer to check for busy */ 813 __u32 handle; 814 815 /** Return busy status (1 if busy, 0 if idle). 816 * The high word is used to indicate on which rings the object 817 * currently resides: 818 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 819 */ 820 __u32 busy; 821 }; 822 823 /** 824 * I915_CACHING_NONE 825 * 826 * GPU access is not coherent with cpu caches. Default for machines without an 827 * LLC. 828 */ 829 #define I915_CACHING_NONE 0 830 /** 831 * I915_CACHING_CACHED 832 * 833 * GPU access is coherent with cpu caches and furthermore the data is cached in 834 * last-level caches shared between cpu cores and the gpu GT. Default on 835 * machines with HAS_LLC. 836 */ 837 #define I915_CACHING_CACHED 1 838 /** 839 * I915_CACHING_DISPLAY 840 * 841 * Special GPU caching mode which is coherent with the scanout engines. 842 * Transparently falls back to I915_CACHING_NONE on platforms where no special 843 * cache mode (like write-through or gfdt flushing) is available. The kernel 844 * automatically sets this mode when using a buffer as a scanout target. 845 * Userspace can manually set this mode to avoid a costly stall and clflush in 846 * the hotpath of drawing the first frame. 847 */ 848 #define I915_CACHING_DISPLAY 2 849 850 struct drm_i915_gem_caching { 851 /** 852 * Handle of the buffer to set/get the caching level of. */ 853 __u32 handle; 854 855 /** 856 * Cacheing level to apply or return value 857 * 858 * bits0-15 are for generic caching control (i.e. the above defined 859 * values). bits16-31 are reserved for platform-specific variations 860 * (e.g. l3$ caching on gen7). */ 861 __u32 caching; 862 }; 863 864 #define I915_TILING_NONE 0 865 #define I915_TILING_X 1 866 #define I915_TILING_Y 2 867 868 #define I915_BIT_6_SWIZZLE_NONE 0 869 #define I915_BIT_6_SWIZZLE_9 1 870 #define I915_BIT_6_SWIZZLE_9_10 2 871 #define I915_BIT_6_SWIZZLE_9_11 3 872 #define I915_BIT_6_SWIZZLE_9_10_11 4 873 /* Not seen by userland */ 874 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 875 /* Seen by userland. */ 876 #define I915_BIT_6_SWIZZLE_9_17 6 877 #define I915_BIT_6_SWIZZLE_9_10_17 7 878 879 struct drm_i915_gem_set_tiling { 880 /** Handle of the buffer to have its tiling state updated */ 881 __u32 handle; 882 883 /** 884 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 885 * I915_TILING_Y). 886 * 887 * This value is to be set on request, and will be updated by the 888 * kernel on successful return with the actual chosen tiling layout. 889 * 890 * The tiling mode may be demoted to I915_TILING_NONE when the system 891 * has bit 6 swizzling that can't be managed correctly by GEM. 892 * 893 * Buffer contents become undefined when changing tiling_mode. 894 */ 895 __u32 tiling_mode; 896 897 /** 898 * Stride in bytes for the object when in I915_TILING_X or 899 * I915_TILING_Y. 900 */ 901 __u32 stride; 902 903 /** 904 * Returned address bit 6 swizzling required for CPU access through 905 * mmap mapping. 906 */ 907 __u32 swizzle_mode; 908 }; 909 910 struct drm_i915_gem_get_tiling { 911 /** Handle of the buffer to get tiling state for. */ 912 __u32 handle; 913 914 /** 915 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 916 * I915_TILING_Y). 917 */ 918 __u32 tiling_mode; 919 920 /** 921 * Returned address bit 6 swizzling required for CPU access through 922 * mmap mapping. 923 */ 924 __u32 swizzle_mode; 925 926 /** 927 * Returned address bit 6 swizzling required for CPU access through 928 * mmap mapping whilst bound. 929 */ 930 __u32 phys_swizzle_mode; 931 }; 932 933 struct drm_i915_gem_get_aperture { 934 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 935 __u64 aper_size; 936 937 /** 938 * Available space in the aperture used by i915_gem_execbuffer, in 939 * bytes 940 */ 941 __u64 aper_available_size; 942 }; 943 944 struct drm_i915_get_pipe_from_crtc_id { 945 /** ID of CRTC being requested **/ 946 __u32 crtc_id; 947 948 /** pipe of requested CRTC **/ 949 __u32 pipe; 950 }; 951 952 #define I915_MADV_WILLNEED 0 953 #define I915_MADV_DONTNEED 1 954 #define __I915_MADV_PURGED 2 /* internal state */ 955 956 struct drm_i915_gem_madvise { 957 /** Handle of the buffer to change the backing store advice */ 958 __u32 handle; 959 960 /* Advice: either the buffer will be needed again in the near future, 961 * or wont be and could be discarded under memory pressure. 962 */ 963 __u32 madv; 964 965 /** Whether the backing store still exists. */ 966 __u32 retained; 967 }; 968 969 /* flags */ 970 #define I915_OVERLAY_TYPE_MASK 0xff 971 #define I915_OVERLAY_YUV_PLANAR 0x01 972 #define I915_OVERLAY_YUV_PACKED 0x02 973 #define I915_OVERLAY_RGB 0x03 974 975 #define I915_OVERLAY_DEPTH_MASK 0xff00 976 #define I915_OVERLAY_RGB24 0x1000 977 #define I915_OVERLAY_RGB16 0x2000 978 #define I915_OVERLAY_RGB15 0x3000 979 #define I915_OVERLAY_YUV422 0x0100 980 #define I915_OVERLAY_YUV411 0x0200 981 #define I915_OVERLAY_YUV420 0x0300 982 #define I915_OVERLAY_YUV410 0x0400 983 984 #define I915_OVERLAY_SWAP_MASK 0xff0000 985 #define I915_OVERLAY_NO_SWAP 0x000000 986 #define I915_OVERLAY_UV_SWAP 0x010000 987 #define I915_OVERLAY_Y_SWAP 0x020000 988 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 989 990 #define I915_OVERLAY_FLAGS_MASK 0xff000000 991 #define I915_OVERLAY_ENABLE 0x01000000 992 993 struct drm_intel_overlay_put_image { 994 /* various flags and src format description */ 995 __u32 flags; 996 /* source picture description */ 997 __u32 bo_handle; 998 /* stride values and offsets are in bytes, buffer relative */ 999 __u16 stride_Y; /* stride for packed formats */ 1000 __u16 stride_UV; 1001 __u32 offset_Y; /* offset for packet formats */ 1002 __u32 offset_U; 1003 __u32 offset_V; 1004 /* in pixels */ 1005 __u16 src_width; 1006 __u16 src_height; 1007 /* to compensate the scaling factors for partially covered surfaces */ 1008 __u16 src_scan_width; 1009 __u16 src_scan_height; 1010 /* output crtc description */ 1011 __u32 crtc_id; 1012 __u16 dst_x; 1013 __u16 dst_y; 1014 __u16 dst_width; 1015 __u16 dst_height; 1016 }; 1017 1018 /* flags */ 1019 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1020 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1021 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1022 struct drm_intel_overlay_attrs { 1023 __u32 flags; 1024 __u32 color_key; 1025 __s32 brightness; 1026 __u32 contrast; 1027 __u32 saturation; 1028 __u32 gamma0; 1029 __u32 gamma1; 1030 __u32 gamma2; 1031 __u32 gamma3; 1032 __u32 gamma4; 1033 __u32 gamma5; 1034 }; 1035 1036 /* 1037 * Intel sprite handling 1038 * 1039 * Color keying works with a min/mask/max tuple. Both source and destination 1040 * color keying is allowed. 1041 * 1042 * Source keying: 1043 * Sprite pixels within the min & max values, masked against the color channels 1044 * specified in the mask field, will be transparent. All other pixels will 1045 * be displayed on top of the primary plane. For RGB surfaces, only the min 1046 * and mask fields will be used; ranged compares are not allowed. 1047 * 1048 * Destination keying: 1049 * Primary plane pixels that match the min value, masked against the color 1050 * channels specified in the mask field, will be replaced by corresponding 1051 * pixels from the sprite plane. 1052 * 1053 * Note that source & destination keying are exclusive; only one can be 1054 * active on a given plane. 1055 */ 1056 1057 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1058 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1059 #define I915_SET_COLORKEY_SOURCE (1<<2) 1060 struct drm_intel_sprite_colorkey { 1061 __u32 plane_id; 1062 __u32 min_value; 1063 __u32 channel_mask; 1064 __u32 max_value; 1065 __u32 flags; 1066 }; 1067 1068 struct drm_i915_gem_wait { 1069 /** Handle of BO we shall wait on */ 1070 __u32 bo_handle; 1071 __u32 flags; 1072 /** Number of nanoseconds to wait, Returns time remaining. */ 1073 __s64 timeout_ns; 1074 }; 1075 1076 struct drm_i915_gem_context_create { 1077 /* output: id of new context*/ 1078 __u32 ctx_id; 1079 __u32 pad; 1080 }; 1081 1082 struct drm_i915_gem_context_destroy { 1083 __u32 ctx_id; 1084 __u32 pad; 1085 }; 1086 1087 struct drm_i915_reg_read { 1088 /* 1089 * Register offset. 1090 * For 64bit wide registers where the upper 32bits don't immediately 1091 * follow the lower 32bits, the offset of the lower 32bits must 1092 * be specified 1093 */ 1094 __u64 offset; 1095 __u64 val; /* Return value */ 1096 }; 1097 /* Known registers: 1098 * 1099 * Render engine timestamp - 0x2358 + 64bit - gen7+ 1100 * - Note this register returns an invalid value if using the default 1101 * single instruction 8byte read, in order to workaround that use 1102 * offset (0x2538 | 1) instead. 1103 * 1104 */ 1105 1106 struct drm_i915_reset_stats { 1107 __u32 ctx_id; 1108 __u32 flags; 1109 1110 /* All resets since boot/module reload, for all contexts */ 1111 __u32 reset_count; 1112 1113 /* Number of batches lost when active in GPU, for this context */ 1114 __u32 batch_active; 1115 1116 /* Number of batches lost pending for execution, for this context */ 1117 __u32 batch_pending; 1118 1119 __u32 pad; 1120 }; 1121 1122 struct drm_i915_gem_userptr { 1123 __u64 user_ptr; 1124 __u64 user_size; 1125 __u32 flags; 1126 #define I915_USERPTR_READ_ONLY 0x1 1127 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1128 /** 1129 * Returned handle for the object. 1130 * 1131 * Object handles are nonzero. 1132 */ 1133 __u32 handle; 1134 }; 1135 1136 struct drm_i915_gem_context_param { 1137 __u32 ctx_id; 1138 __u32 size; 1139 __u64 param; 1140 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1141 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1142 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1143 __u64 value; 1144 }; 1145 1146 #endif /* _I915_DRM_H_ */ 1147