1/* ldst-reg-reg-offset.s Test file for AArch64 load-store reg. (reg.offset)
2   instructions.
3
4   Copyright (C) 2011-2014 Free Software Foundation, Inc.
5   Contributed by ARM Ltd.
6
7   This file is part of GAS.
8
9   GAS is free software; you can redistribute it and/or modify
10   it under the terms of the GNU General Public License as published by
11   the Free Software Foundation; either version 3 of the license, or
12   (at your option) any later version.
13
14   GAS is distributed in the hope that it will be useful,
15   but WITHOUT ANY WARRANTY; without even the implied warranty of
16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17   GNU General Public License for more details.
18
19   You should have received a copy of the GNU General Public License
20   along with this program; see the file COPYING3. If not,
21   see <http://www.gnu.org/licenses/>.  */
22
23/* Only instructions loading from/storing to FP/SIMD register are
24   tested here.  */
25
26	.macro	op3_32 op, reg, ext, imm
27	.ifc \imm, -1
28	\op	\reg\()7, [sp, w7, \ext]
29	.else
30	\op	\reg\()7, [sp, w7, \ext #\imm]
31	.endif
32	.endm
33
34	.macro	op3_64 op, reg, ext, imm
35	.ifc \imm, -1
36	\op	\reg\()7, [sp, x7, \ext]
37	.else
38	\op	\reg\()7, [sp, x7, \ext #\imm]
39	.endif
40	.endm
41
42	.macro	op3 op, reg, ext, imm=-1
43	.ifc \ext, uxtw
44	op3_32	\op, \reg, \ext, \imm
45	.endif
46	.ifc \ext, sxtw
47	op3_32	\op, \reg, \ext, \imm
48	.endif
49	.ifc \ext, lsl
50		.ifnc \imm, -1
51		// shift <amount> is mandatory when 'lsl' is used
52		op3_64	\op, \reg, \ext, \imm
53		.else
54		// absent shift; lsl by default
55		\op	\reg\()7, [sp, x7]
56		.endif
57	.endif
58	.ifc \ext, sxtx
59	op3_64	\op, \reg, \ext, \imm
60	.endif
61	.endm
62
63	.macro shift op, ext
64	op3	\op, b, \ext
65	op3	\op, b, \ext, 0
66	op3	\op, h, \ext, 0
67	op3	\op, h, \ext, 1
68	op3	\op, s, \ext, 0
69	op3	\op, s, \ext, 2
70	op3	\op, d, \ext, 0
71	op3	\op, d, \ext, 3
72	op3	\op, q, \ext, 0
73	op3	\op, q, \ext, 4
74	.endm
75
76	.macro extend op
77	.irp ext, uxtw, lsl, sxtw, sxtx
78	shift	\op, \ext
79	.endr
80	.endm
81
82	.macro ld_or_st op
83	extend	\op
84	.endm
85
86func:
87	ld_or_st	str
88	ld_or_st	ldr
89
90	/* When the index register is of register 31, it should be ZR.  */
91	ldr	x1, [sp, xzr, sxtx #3]
92	str	x1, [sp, xzr, sxtx #3]
93	ldr	w1, [sp, wzr, sxtw #2]
94	str	w1, [sp, wzr, sxtw #2]
95