1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
4
5declare double @llvm.fabs.f64(double %Val)
6declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone
7
8; FUNC-LABEL: {{^}}fract_f64:
9; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
10; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
11; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
12; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
13; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
14; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
15; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
16; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
17; CI: buffer_store_dwordx2 [[FRC]]
18define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
19  %val = load double, double addrspace(1)* %src, align 4
20  %fract = call double @llvm.AMDGPU.fract.f64(double %val) nounwind readnone
21  store double %fract, double addrspace(1)* %out, align 4
22  ret void
23}
24
25; FUNC-LABEL: {{^}}fract_f64_neg:
26; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
27; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
28; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
29; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
30; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
31; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
32; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
33; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
34; CI: buffer_store_dwordx2 [[FRC]]
35define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
36  %val = load double, double addrspace(1)* %src, align 4
37  %neg = fsub double 0.0, %val
38  %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
39  store double %fract, double addrspace(1)* %out, align 4
40  ret void
41}
42
43; FUNC-LABEL: {{^}}fract_f64_neg_abs:
44; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
45; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
46; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
47; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
48; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
49; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
50; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
51; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
52; CI: buffer_store_dwordx2 [[FRC]]
53define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
54  %val = load double, double addrspace(1)* %src, align 4
55  %abs = call double @llvm.fabs.f64(double %val)
56  %neg = fsub double 0.0, %abs
57  %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
58  store double %fract, double addrspace(1)* %out, align 4
59  ret void
60}
61