1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI  -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4
5; FUNC-LABEL: {{^}}read_workdim:
6; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
7; EG: MOV * [[VAL]], KC0[2].Z
8
9; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
10; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
11; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
12; GCN-NOHSA: buffer_store_dword [[VVAL]]
13define void @read_workdim(i32 addrspace(1)* %out) {
14entry:
15  %0 = call i32 @llvm.AMDGPU.read.workdim() #0
16  store i32 %0, i32 addrspace(1)* %out
17  ret void
18}
19
20; FUNC-LABEL: {{^}}read_workdim_known_bits:
21; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
22; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
23; GCN-NOT: 0xff
24; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
25; GCN: buffer_store_dword [[VVAL]]
26define void @read_workdim_known_bits(i32 addrspace(1)* %out) {
27entry:
28  %dim = call i32 @llvm.AMDGPU.read.workdim() #0
29  %shl = shl i32 %dim, 24
30  %shr = lshr i32 %shl, 24
31  store i32 %shr, i32 addrspace(1)* %out
32  ret void
33}
34
35declare i32 @llvm.AMDGPU.read.workdim() #0
36
37attributes #0 = { readnone }
38