1#!/usr/bin/env python2.7
2
3# Copyright 2015, ARM Limited
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9#   * Redistributions of source code must retain the above copyright notice,
10#     this list of conditions and the following disclaimer.
11#   * Redistributions in binary form must reproduce the above copyright notice,
12#     this list of conditions and the following disclaimer in the documentation
13#     and/or other materials provided with the distribution.
14#   * Neither the name of ARM Limited nor the names of its contributors may be
15#     used to endorse or promote products derived from this software without
16#     specific prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
19# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
22# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29import os
30import sys
31import argparse
32import re
33import util
34
35copyright_header = """// Copyright 2015, ARM Limited
36// All rights reserved.
37//
38// Redistribution and use in source and binary forms, with or without
39// modification, are permitted provided that the following conditions are met:
40//
41//   * Redistributions of source code must retain the above copyright notice,
42//     this list of conditions and the following disclaimer.
43//   * Redistributions in binary form must reproduce the above copyright notice,
44//     this list of conditions and the following disclaimer in the documentation
45//     and/or other materials provided with the distribution.
46//   * Neither the name of ARM Limited nor the names of its contributors may be
47//     used to endorse or promote products derived from this software without
48//     specific prior written permission.
49//
50// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
51// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
52// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
53// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
54// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
55// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
56// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
57// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
58// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60
61"""
62
63master_trace_header = """
64// This file holds the expected results for the instructions tested by
65// test-simulator-a64.
66//
67// If you update input lists in test-simulator-inputs-a64.h, or add a new test
68// to test-simulator-a64.cc, please run tools/generate_simulator_traces.py on a
69// reference platform to regenerate this file and trace files.
70//
71
72#ifndef VIXL_TEST_SIMULATOR_TRACES_A64_H_
73#define VIXL_TEST_SIMULATOR_TRACES_A64_H_
74
75#include <stdint.h>
76
77// To add a new simulator test to test-simulator-a64.cc, add dummy array(s)
78// below to build test-simulator-a64 for reference platform. Then, run
79// tools/generate_simulator_traces.py on a reference platform to regenerate this
80// file and traces files.
81
82// ---------------------------------------------------------------------
83// ADD DUMMY ARRAYS FOR NEW SIMULATOR TEST HERE.
84// ---------------------------------------------------------------------
85const uint64_t kExpected_dummy_64[] = { 0 };
86const size_t kExpectedCount_dummy_64 = 0;
87
88const uint32_t kExpected_dummy_32[] = { 0 };
89const size_t kExpectedCount_dummy_32 = 0;
90
91// ---------------------------------------------------------------------
92// Simulator test trace output files.
93// ---------------------------------------------------------------------
94"""
95master_trace_footer = """
96#endif  // VIXL_TEST_SIMULATOR_TRACES_A64_H_
97"""
98
99trace_header = """
100// ---------------------------------------------------------------------
101// This file is auto generated using tools/generate_simulator_traces.py.
102//
103// PLEASE DO NOT EDIT.
104// ---------------------------------------------------------------------
105"""
106
107def BuildOptions(root):
108  result = argparse.ArgumentParser(description = 'Simulator test generator.')
109  result.add_argument('--runner', action='store', default=root+'/test-runner',
110                      help='The test executable to run.')
111  result.add_argument('--out', action='store',
112                      default='test/test-simulator-traces-a64.h')
113  return result.parse_args()
114
115
116if __name__ == '__main__':
117  # $ROOT/tools/generate_simulator_traces.py
118  root_dir = os.path.dirname(os.path.dirname(os.path.abspath(sys.argv[0])))
119  os.chdir(root_dir)
120
121  args = BuildOptions(root_dir)
122
123  # Run each simulator test (SIM_*) with the --sim_test_trace option, and use
124  # the output to create the traces header (from --out). In addition, the
125  # test-simulator-traces-a64.h file, the master trace file, which includes all
126  # other trace files is generated.
127
128  # Create master trace file.
129  master_trace_f = open(args.out, 'w')
130  master_trace_f.write(copyright_header)
131  master_trace_f.write(master_trace_header)
132  master_trace_f.write('\n\n')
133
134  # Find the simulator tests.
135  status, output = util.getstatusoutput(args.runner + ' --list')
136  if status != 0: util.abort('Failed to list all tests')
137  tests = filter(lambda t: 'SIM_' in t, output.split())
138  tests.sort()
139
140  for test in tests:
141    # Run each test.
142    print 'Generating trace for ' + test;
143    cmd = ' '.join([args.runner, '--sim_test_trace', test])
144    status, output = util.getstatusoutput(cmd)
145    if status != 0: util.abort('Failed to run ' + cmd + '.')
146
147    # Create a new trace header file.
148    trace_filename = test.lower().replace('_', '-') + "-trace-a64.h"
149    trace_f =  open("test/traces/a64/" + trace_filename, 'w')
150    trace_f.write(copyright_header)
151    trace_f.write(trace_header)
152    trace_f.write('\n')
153    trace_f.write("#ifndef VIXL_" + test.upper() + "_TRACE_A64_H_\n")
154    trace_f.write("#define VIXL_" + test.upper() + "_TRACE_A64_H_\n")
155    trace_f.write('\n')
156    trace_f.write(output)
157    trace_f.write('\n')
158    trace_f.write('\n' + "#endif  // VIXL_" + test.upper() + "_TRACE_A64_H_" + '\n')
159    trace_f.close()
160
161    # Update master trace file.
162    master_trace_f.write('#include \"traces/a64/' + trace_filename + '\"\n')
163
164# Close master trace file.
165  master_trace_f.write(master_trace_footer)
166  master_trace_f.close()
167  print 'Trace generation COMPLETE'
168