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Searched refs:AT (Results 1 – 18 of 18) sorted by relevance

/art/runtime/interpreter/mterp/mips64/
Dheader.S157 sll AT, \reg, 7
158 daddu AT, rIBASE, AT
159 jic AT, 0
172 dlsa AT, \vreg, rFP, 2
173 lw \reg, 0(AT)
178 dlsa AT, \vreg, rFP, 2
179 lwu \reg, 0(AT)
184 dlsa AT, \vreg, rFP, 2
185 lwc1 \reg, 0(AT)
190 dlsa AT, \vreg, rFP, 2
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/art/runtime/interpreter/mterp/mips/
Dheader.S76 #define AT $$at /* assembler temp */ macro
275 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \
276 .set noat; l.s rd, (AT); .set at
279 sll AT, rix, 2; \
280 addu t8, rFP, AT; \
282 addu t8, rREFS, AT; \
287 sll AT, rix, 2; \
288 addu t8, rFP, AT; \
291 addu t8, rREFS, AT; \
298 sll AT, rix, 2; \
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/art/compiler/optimizing/
Dintrinsics_mips.cc285 __ LoadConst32(AT, 0x00FF00FF); in GenReverse()
286 __ And(TMP, out, AT); in GenReverse()
289 __ And(out, out, AT); in GenReverse()
296 __ LoadConst32(AT, 0x0F0F0F0F); in GenReverse()
297 __ And(TMP, out, AT); in GenReverse()
300 __ And(out, out, AT); in GenReverse()
302 __ LoadConst32(AT, 0x33333333); in GenReverse()
303 __ And(TMP, out, AT); in GenReverse()
306 __ And(out, out, AT); in GenReverse()
308 __ LoadConst32(AT, 0x55555555); in GenReverse()
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Dintrinsics_mips64.cc430 __ Dsra32(AT, in, 31); in GenAbsInteger()
431 __ Xor(out, in, AT); in GenAbsInteger()
432 __ Dsubu(out, out, AT); in GenAbsInteger()
434 __ Sra(AT, in, 31); in GenAbsInteger()
435 __ Xor(out, in, AT); in GenAbsInteger()
436 __ Subu(out, out, AT); in GenAbsInteger()
608 __ Slt(AT, rhs, lhs); in GenMinMax()
610 __ Seleqz(out, lhs, AT); in GenMinMax()
611 __ Selnez(AT, rhs, AT); in GenMinMax()
613 __ Selnez(out, lhs, AT); in GenMinMax()
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Dcode_generator_mips.cc595 __ MoveFromFpuHigh(AT, f1); in EmitSwap()
599 __ Move(r2_h, AT); in EmitSwap()
979 Register card = AT; in MarkGCCard()
1006 blocked_core_registers_[AT] = true; in SetupBlockedRegisters()
1099 __ LoadConst32(AT, mirror::Class::kStatusInitialized); in GenerateClassInitializationCheck()
1100 __ Blt(TMP, AT, slow_path->GetEntryLabel()); in GenerateClassInitializationCheck()
1349 __ Sltiu(AT, dst_low, low); in HandleBinaryOp()
1354 __ Sltu(AT, dst_low, TMP); in HandleBinaryOp()
1367 __ Addu(dst_high, dst_high, AT); in HandleBinaryOp()
1579 __ Nor(AT, ZERO, rhs_reg); in HandleShift()
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Dcode_generator_mips64.cc680 GpuRegister gpr = AT; in MoveLocation()
877 GpuRegister card = AT; in MarkGCCard()
905 blocked_core_registers_[AT] = true; in SetupBlockedRegisters()
982 __ LoadConst32(AT, mirror::Class::kStatusInitialized); in GenerateClassInitializationCheck()
983 __ Bltc(TMP, AT, slow_path->GetEntryLabel()); in GenerateClassInitializationCheck()
1715 rhs = AT; in VisitCompare()
1721 rhs = AT; in VisitCompare()
2018 __ Sra(AT, TMP, 31); in GenerateDivRemWithAnyConstant()
2019 __ Subu(AT, TMP, AT); in GenerateDivRemWithAnyConstant()
2021 __ MulR6(TMP, AT, TMP); in GenerateDivRemWithAnyConstant()
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/art/compiler/utils/mips/
Dassembler_mips.cc1389 CHECK_NE(temp, AT); // Must not use AT as temp, as not to overwrite the loaded value. in StoreConst32ToOffset()
1390 LoadConst32(AT, offset); in StoreConst32ToOffset()
1391 Addu(AT, AT, base); in StoreConst32ToOffset()
1392 base = AT; in StoreConst32ToOffset()
1409 CHECK_NE(temp, AT); // Must not use AT as temp, as not to overwrite the loaded value. in StoreConst64ToOffset()
1410 LoadConst32(AT, offset); in StoreConst64ToOffset()
1411 Addu(AT, AT, base); in StoreConst64ToOffset()
1412 base = AT; in StoreConst64ToOffset()
1604 CHECK_NE(indirect_reg, AT); in Branch()
2080 Lui(AT, High16Bits(offset)); in EmitBranch()
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Dassembler_mips_test.cc58 registers_.push_back(new mips::Register(mips::AT)); in SetUpHelpers()
91 secondary_register_names_.emplace(mips::Register(mips::AT), "at"); in SetUpHelpers()
Dassembler_mips.h362 void Addiu32(Register rt, Register rs, int32_t value, Register rtmp = AT);
/art/runtime/arch/mips/
Dregisters_mips.h31 AT = 1, // Assembler temporary. enumerator
/art/runtime/arch/mips64/
Dregisters_mips64.h31 AT = 1, // Assembler temporary. enumerator
/art/compiler/utils/mips64/
Dassembler_mips64.cc1287 CHECK_NE(indirect_reg, AT); in Branch()
1717 Auipc(AT, High16Bits(offset)); in EmitBranch()
1718 Jic(AT, Low16Bits(offset)); in EmitBranch()
1724 Auipc(AT, High16Bits(offset)); in EmitBranch()
1725 Jic(AT, Low16Bits(offset)); in EmitBranch()
1808 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); in LoadFromOffset()
1809 Daddu(AT, AT, base); in LoadFromOffset()
1810 base = AT; in LoadFromOffset()
1853 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); in LoadFpuFromOffset()
1854 Daddu(AT, AT, base); in LoadFpuFromOffset()
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Dassembler_mips64_test.cc82 registers_.push_back(new mips64::GpuRegister(mips64::AT)); in SetUpHelpers()
115 secondary_register_names_.emplace(mips64::GpuRegister(mips64::AT), "at"); in SetUpHelpers()
Dassembler_mips64.h327 void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64
/art/compiler/jni/quick/mips64/
Dcalling_convention_mips64.cc148 return Mips64ManagedRegister::FromGpuRegister(AT); in ReturnScratchRegister()
/art/runtime/interpreter/mterp/out/
Dmterp_mips.S83 #define AT $at /* assembler temp */ macro
282 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \
283 .set noat; l.s rd, (AT); .set at
286 sll AT, rix, 2; \
287 addu t8, rFP, AT; \
289 addu t8, rREFS, AT; \
294 sll AT, rix, 2; \
295 addu t8, rFP, AT; \
298 addu t8, rREFS, AT; \
305 sll AT, rix, 2; \
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Dmterp_mips64.S164 sll AT, \reg, 7
165 daddu AT, rIBASE, AT
166 jic AT, 0
179 dlsa AT, \vreg, rFP, 2
180 lw \reg, 0(AT)
185 dlsa AT, \vreg, rFP, 2
186 lwu \reg, 0(AT)
191 dlsa AT, \vreg, rFP, 2
192 lwc1 \reg, 0(AT)
197 dlsa AT, \vreg, rFP, 2
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/art/compiler/jni/quick/mips/
Dcalling_convention_mips.cc182 return MipsManagedRegister::FromCoreRegister(AT); in ReturnScratchRegister()