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Searched refs:Out (Results 1 – 22 of 22) sorted by relevance

/art/compiler/optimizing/
Dintrinsics_mips.cc122 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
164 Register out_lo = locations->Out().AsRegisterPairLow<Register>(); in MoveFPToInt()
165 Register out_hi = locations->Out().AsRegisterPairHigh<Register>(); in MoveFPToInt()
170 Register out = locations->Out().AsRegister<Register>(); in MoveFPToInt()
203 FRegister out = locations->Out().AsFpuRegister<FRegister>(); in MoveIntToFP()
259 Register out = locations->Out().AsRegister<Register>(); in GenReverse()
273 Register out = locations->Out().AsRegister<Register>(); in GenReverse()
319 Register out_lo = locations->Out().AsRegisterPairLow<Register>(); in GenReverse()
320 Register out_hi = locations->Out().AsRegisterPairHigh<Register>(); in GenReverse()
446 Register out = locations->Out().AsRegister<Register>(); in GenNumberOfLeadingZeroes()
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Dintrinsics_mips64.cc111 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
151 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in MoveFPToInt()
188 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>(); in MoveIntToFP()
227 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in GenReverseBytes()
279 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in GenNumberOfLeadingZeroes()
310 Location out = locations->Out(); in GenNumberOfTrailingZeroes()
349 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in GenReverse()
390 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>(); in MathAbsFP()
427 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in GenAbsInteger()
464 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>(); in GenMinMaxFP()
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Dintrinsics_arm.cc86 Location output = locations->Out(); in MoveFPToInt()
98 Location output = locations->Out(); in MoveIntToFP()
156 Register out = locations->Out().AsRegister<Register>(); in GenNumberOfLeadingZeros()
199 Register out = locations->Out().AsRegister<Register>(); in GenNumberOfTrailingZeros()
245 Location out = locations->Out(); in MathAbsFP()
285 Location output = locations->Out(); in GenAbsInteger()
334 Register out = locations->Out().AsRegister<Register>(); in GenMinMax()
375 __ vsqrtd(FromLowSToD(locations->Out().AsFpuRegisterPairLow<SRegister>()), in VisitMathSqrt()
386 __ ldrsb(invoke->GetLocations()->Out().AsRegister<Register>(), in VisitMemoryPeekByte()
397 __ ldr(invoke->GetLocations()->Out().AsRegister<Register>(), in VisitMemoryPeekIntNative()
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Dintrinsics_arm64.cc123 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
187 Location output = locations->Out(); in MoveFPToInt()
194 Location output = locations->Out(); in MoveIntToFP()
239 Location out = locations->Out(); in GenReverseBytes()
295 Location out = locations->Out(); in GenNumberOfLeadingZeros()
322 Location out = locations->Out(); in GenNumberOfTrailingZeros()
350 Location out = locations->Out(); in GenReverse()
379 Register dst = RegisterFrom(instr->GetLocations()->Out(), type); in GenBitCount()
414 Location out = locations->Out(); in MathAbsFP()
450 Location output = locations->Out(); in GenAbsInteger()
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Dssa_liveness_analysis.cc125 if (locations != nullptr && locations->Out().IsValid()) { in NumberInstructions()
143 if (locations != nullptr && locations->Out().IsValid()) { in NumberInstructions()
183 bool has_out_location = input->GetLocations()->Out().IsValid(); in RecursivelyProcessInputs()
285 DCHECK(!current->GetLocations()->Out().IsValid()); in ComputeLiveRanges()
490 Location out = locations->Out(); in FindHintAtDefinition()
548 return defined_by->GetLocations()->Out(); in ToLocation()
Dcode_generator_mips.cc244 Location out = locations->Out(); in EmitNativeCode()
280 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
296 mips_codegen->MoveLocation(locations->Out(), in EmitNativeCode()
383 Location object_class = instruction_->IsCheckCast() ? locations->GetTemp(0) : locations->Out(); in EmitNativeCode()
386 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
412 mips_codegen->MoveLocation(locations->Out(), ret_loc, ret_type); in EmitNativeCode()
1190 Register dst = locations->Out().AsRegister<Register>(); in HandleBinaryOp()
1234 Register dst_high = locations->Out().AsRegisterPairHigh<Register>(); in HandleBinaryOp()
1235 Register dst_low = locations->Out().AsRegisterPairLow<Register>(); in HandleBinaryOp()
1376 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in HandleBinaryOp()
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Dcode_generator_mips64.cc199 Location out = locations->Out(); in EmitNativeCode()
235 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
250 mips64_codegen->MoveLocation(locations->Out(), in EmitNativeCode()
335 Location object_class = instruction_->IsCheckCast() ? locations->GetTemp(0) : locations->Out(); in EmitNativeCode()
338 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
363 mips64_codegen->MoveLocation(locations->Out(), ret_loc, ret_type); in EmitNativeCode()
1066 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); in HandleBinaryOp()
1124 FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>(); in HandleBinaryOp()
1173 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); in HandleShift()
1295 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in VisitArrayGet()
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Dintrinsics_utils.h66 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
Dintrinsics_x86.cc113 Location output = locations->Out(); in MoveFPToInt()
128 Location output = locations->Out(); in MoveIntToFP()
197 Register out = locations->Out().AsRegister<Register>(); in GenReverseBytes()
231 Location output = locations->Out(); in VisitLongReverseBytes()
277 Location output = locations->Out(); in MathAbsFP()
334 Location output = locations->Out(); in GenAbsInteger()
365 Location output = locations->Out(); in GenAbsLong()
410 Location out_loc = locations->Out(); in GenMinMaxFP()
578 DCHECK(locations->Out().Equals(op1_loc)); in GenMinMax()
585 Location output = locations->Out(); in GenMinMax()
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Dintrinsics_x86_64.cc100 Location output = locations->Out(); in MoveFPToInt()
106 Location output = locations->Out(); in MoveIntToFP()
149 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in GenReverseBytes()
211 Location output = locations->Out(); in MathAbsFP()
254 Location output = locations->Out(); in GenAbsInteger()
298 Location out_loc = locations->Out(); in GenMinMaxFP()
432 DCHECK(locations->Out().Equals(op1_loc)); in GenMinMax()
436 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in GenMinMax()
510 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>(); in VisitMathSqrt()
524 Location out = invoke->GetLocations()->Out(); in InvokeOutOfLineIntrinsic()
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Dcode_generator_arm.cc221 Location out = locations->Out(); in EmitNativeCode()
224 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0)); in EmitNativeCode()
255 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
267 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0)); in EmitNativeCode()
287 : locations->Out(); in EmitNativeCode()
289 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
316 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0)); in EmitNativeCode()
1520 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType()); in VisitSelect()
1575 Register out = locations->Out().AsRegister<Register>(); in HandleCondition()
1589 __ mov(locations->Out().AsRegister<Register>(), ShifterOperand(1), in HandleCondition()
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Dcommon_arm64.h71 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
95 return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputFPRegister()
Dcode_generator_x86_64.cc252 Location out = locations->Out(); in EmitNativeCode()
288 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
302 x86_64_codegen->Move(locations->Out(), Location::RegisterLocation(RAX)); in EmitNativeCode()
321 : locations->Out(); in EmitNativeCode()
324 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
362 x86_64_codegen->Move(locations->Out(), Location::RegisterLocation(RAX)); in EmitNativeCode()
1579 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitSelect()
1624 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType()); in VisitSelect()
1673 CpuRegister reg = locations->Out().AsRegister<CpuRegister>(); in HandleCondition()
1858 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in VisitCompare()
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Dcode_generator_x86.cc211 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
225 x86_codegen->Move32(locations->Out(), Location::RegisterLocation(EAX)); in EmitNativeCode()
265 Location out = locations->Out(); in EmitNativeCode()
302 : locations->Out(); in EmitNativeCode()
304 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
342 x86_codegen->Move32(locations->Out(), Location::RegisterLocation(EAX)); in EmitNativeCode()
1548 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitSelect()
1611 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType()); in VisitSelect()
1675 Register reg = locations->Out().AsRegister<Register>(); in HandleCondition()
2081 Location out = locations->Out(); in VisitNeg()
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Dcode_generator.cc102 if (locations->Out().IsUnallocated() in CheckTypeConsistency()
103 && (locations->Out().GetPolicy() == Location::kSameAsFirstInput)) { in CheckTypeConsistency()
108 DCHECK(CheckType(instruction->GetType(), locations->Out())) in CheckTypeConsistency()
110 << " " << locations->Out(); in CheckTypeConsistency()
476 MoveLocation(locations->Out(), calling_convention.GetReturnLocation(field_type), field_type); in GenerateUnresolvedFieldAccess()
Dcode_generator_arm64.cc305 Location out = locations->Out(); in EmitNativeCode()
341 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
354 arm64_codegen->MoveLocation(locations->Out(), calling_convention.GetReturnLocation(type), type); in EmitNativeCode()
440 : locations->Out(); in EmitNativeCode()
442 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
466 arm64_codegen->MoveLocation(locations->Out(), ret_loc, ret_type); in EmitNativeCode()
1628 Location out = locations->Out(); in HandleFieldGet()
2054 Location out = locations->Out(); in VisitArrayGet()
2484 Register res = RegisterFrom(locations->Out(), instruction->GetType()); in HandleCondition()
3144 Location out_loc = locations->Out(); in VisitInstanceOf()
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Dlocations.h531 Location Out() const { return output_; } in Out() function
Dregister_allocator.cc362 Location output = locations->Out(); in ProcessInstruction()
755 if (!locations->OutputCanOverlapWithInputs() && locations->Out().IsUnallocated()) { in TryAllocateFreeReg()
1796 location_source = defined_by->GetLocations()->Out(); in ConnectSplitSiblings()
1839 Location location = locations->Out(); in Resolve()
Dregister_allocator_test.cc748 ASSERT_EQ(first_sub->GetLocations()->Out().GetPolicy(), Location::kSameAsFirstInput); in TEST_F()
749 ASSERT_EQ(second_sub->GetLocations()->Out().GetPolicy(), Location::kSameAsFirstInput); in TEST_F()
Dssa_liveness_analysis.h517 DCHECK(defined_by_->GetLocations()->Out().IsValid()); in FirstUseAfter()
931 Location location = locations->Out(); in DefinitionRequiresRegister()
Dgraph_visualizer.cc548 DumpLocation(attr, locations->Out()); in PrintInstruction()
/art/tools/dexfuzz/
DREADME88 |Iterations|VerifyFail|MutateFail|Timed Out |Successful|Divergence|
99 Timed Out - mutated files that timed out for one or more backends.