| /art/runtime/arch/mips/ |
| D | registers_mips.cc | 31 if (rhs >= ZERO && rhs <= RA) { in operator <<()
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| D | registers_mips.h | 61 RA = 31, // Return address. enumerator
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| D | quick_method_frame_info_mips.h | 29 (1 << art::mips::RA);
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| D | quick_entrypoints_mips.S | 423 sw $ra, 0($t0) # Store RA per the compiler ABI
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 61 RA = 31, // Return address. enumerator
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| D | quick_method_frame_info_mips64.h | 53 (type == Runtime::kSaveAll ? kMips64CalleeSaveAllSpills : 0) | (1 << art::mips64::RA); in Mips64CalleeSaveCoreSpills()
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| D | quick_entrypoints_mips64.S | 1834 jal artInstrumentationMethodEntryFromCode # (Method*, Object*, Thread*, RA)
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA; in CoreSpillMask()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA; in CoreSpillMask()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 595 Jalr(RA, rs); in Jalr()
2052 Addiu(lhs, RA, offset); in EmitBranch()
2077 Push(RA); in EmitBranch()
2082 Addu(AT, AT, RA); in EmitBranch()
2083 Lw(RA, SP, 0); in EmitBranch()
2093 Push(RA); in EmitBranch()
2098 Addu(AT, AT, RA); in EmitBranch()
2099 Lw(RA, SP, 0); in EmitBranch()
2108 Addu(lhs, AT, RA); in EmitBranch()
2452 StoreToOffset(kStoreWord, RA, SP, stack_offset); in BuildFrame()
[all …]
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| D | assembler_mips_test.cc | 88 registers_.push_back(new mips::Register(mips::RA)); in SetUpHelpers()
121 secondary_register_names_.emplace(mips::Register(mips::RA), "ra"); in SetUpHelpers()
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| /art/compiler/optimizing/ |
| D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| D | code_generator_mips64.cc | 423 AddAllocatedRegister(Location::RegisterLocation(RA)); in CodeGeneratorMIPS64()
620 __ Jr(RA); in GenerateFrameExit()
901 blocked_core_registers_[RA] = true; in SetupBlockedRegisters()
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| D | code_generator_mips.cc | 477 AddAllocatedRegister(Location::RegisterLocation(RA)); in CodeGeneratorMIPS()
796 __ Jr(RA); in GenerateFrameExit()
1002 blocked_core_registers_[RA] = true; in SetupBlockedRegisters()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 526 Jalr(RA, rs); in Jalr()
1991 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); in BuildFrame()
1992 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
2038 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset); in RemoveFrame()
2039 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
2045 Jr(RA); in RemoveFrame()
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| D | assembler_mips64_test.cc | 112 registers_.push_back(new mips64::GpuRegister(mips64::RA)); in SetUpHelpers()
145 secondary_register_names_.emplace(mips64::GpuRegister(mips64::RA), "ra"); in SetUpHelpers()
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