| /art/compiler/optimizing/ |
| D | code_generator_mips.cc | 1469 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
1481 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
1581 __ Srlv(TMP, TMP, AT); in HandleShift() local
1593 __ Srlv(dst_low, lhs_low, rhs_reg); in HandleShift() local
1600 __ Srlv(dst_high, lhs_high, rhs_reg); in HandleShift() local
1604 __ Srlv(dst_low, lhs_low, rhs_reg); in HandleShift() local
1612 __ Srlv(TMP, lhs_low, rhs_reg); in HandleShift() local
1616 __ Srlv(TMP, lhs_high, rhs_reg); in HandleShift() local
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| D | intrinsics_mips.cc | 2340 __ Srlv(out_hi, AT, TMP); in GenHighestOneBit() local
2347 __ Srlv(out_lo, AT, TMP); in GenHighestOneBit() local
2364 __ Srlv(AT, AT, TMP); // Srlv shifts in the range of [0;31] bits (lower 5 bits of arg). in GenHighestOneBit() local
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| D | code_generator_mips64.cc | 1235 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 374 TEST_F(AssemblerMIPSTest, Srlv) { in TEST_F() argument
375 DriverStr(RepeatRRR(&mips::MipsAssembler::Srlv, "srlv ${reg1}, ${reg2}, ${reg3}"), "Srlv"); in TEST_F()
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| D | assembler_mips.h | 172 void Srlv(Register rd, Register rt, Register rs);
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| D | assembler_mips.cc | 391 void MipsAssembler::Srlv(Register rd, Register rt, Register rs) { in Srlv() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 916 TEST_F(AssemblerMIPS64Test, Srlv) { in TEST_F() argument
917 DriverStr(RepeatRRR(&mips64::Mips64Assembler::Srlv, "srlv ${reg1}, ${reg2}, ${reg3}"), "srlv"); in TEST_F()
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| D | assembler_mips64.h | 169 void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
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| D | assembler_mips64.cc | 364 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv() function in art::mips64::Mips64Assembler
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