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Searched refs:SCR (Results 1 – 9 of 9) sorted by relevance

/device/google/contexthub/firmware/src/platform/stm32f4xx/
Dpwr.c246 SCB->SCR &=~ SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
249 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
252 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
256 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
260 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
Dplatform.c241 SCB->SCR &=~ SCB_SCR_SLEEPONEXIT_Msk; in platInitialize()
/device/google/contexthub/firmware/inc/platform/stm32f4xx/cmsis/
Dcore_cm0.h340 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_cm0plus.h355 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_sc000.h346 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_cm3.h354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_sc300.h354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_cm4.h401 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_cm7.h416 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member