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Searched refs:__I (Results 1 – 7 of 7) sorted by relevance

/device/google/contexthub/firmware/inc/platform/stm32f4xx/cmsis/
Dcore_cm3.h198 #define __I volatile /*!< Defines 'read only' permissions */ macro
200 #define __I volatile const /*!< Defines 'read only' permissions */
350__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
364__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
365__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
366__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
367__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
368__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
576__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
615__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
[all …]
Dcore_sc300.h198 #define __I volatile /*!< Defines 'read only' permissions */ macro
200 #define __I volatile const /*!< Defines 'read only' permissions */
350__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
364__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
365__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
366__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
367__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
368__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
571__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
595__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
[all …]
Dcore_cm4.h244 #define __I volatile /*!< Defines 'read only' permissions */ macro
246 #define __I volatile const /*!< Defines 'read only' permissions */
397__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
411__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
412__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
413__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
414__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
415__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
615__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
655__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
[all …]
Dcore_cm7.h259 #define __I volatile /*!< Defines 'read only' permissions */ macro
261 #define __I volatile const /*!< Defines 'read only' permissions */
412__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
426__I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
427__I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
428__I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
429__I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
430__I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
432__I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register …
433__I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register …
[all …]
Dcore_cm0plus.h203 #define __I volatile /*!< Defines 'read only' permissions */ macro
205 #define __I volatile const /*!< Defines 'read only' permissions */
347__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
465__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
512__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register …
Dcore_sc000.h198 #define __I volatile /*!< Defines 'read only' permissions */ macro
200 #define __I volatile const /*!< Defines 'read only' permissions */
342__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
484__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
531__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register …
Dcore_cm0.h193 #define __I volatile /*!< Defines 'read only' permissions */ macro
195 #define __I volatile const /*!< Defines 'read only' permissions */
336__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
444__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …