Searched refs:__O (Results 1 – 7 of 7) sorted by relevance
263 #define __O volatile /*!< Defines 'write only' permissions */ macro392 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…438 …__O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Regi…444 …__O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU …446 …__O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU …447 …__O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC …448 …__O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way …449 …__O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU …450 …__O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC …451 …__O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way …[all …]
202 #define __O volatile /*!< Defines 'write only' permissions */ macro330 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…662 __O union664 …__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit …665 …__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit …666 …__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit …675 …__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register …679 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register …1155 …__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
202 #define __O volatile /*!< Defines 'write only' permissions */ macro330 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…642 __O union644 …__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit …645 …__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit …646 …__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit …655 …__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register …659 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register …1135 …__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
248 #define __O volatile /*!< Defines 'write only' permissions */ macro377 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…702 __O union704 …__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit …705 …__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit …706 …__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit …715 …__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register …719 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register …1301 …__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
197 #define __O volatile /*!< Defines 'write only' permissions */ macro
207 #define __O volatile /*!< Defines 'write only' permissions */ macro
202 #define __O volatile /*!< Defines 'write only' permissions */ macro