| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 260 case ISD::ADDE: { in selectNode()
263 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
268 if (Opcode == ISD::ADDE) { in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 240 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
725 case ISD::ADDE: { in selectNode()
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| D | MipsSEISelLowering.cpp | 142 setTargetDAGCombine(ISD::ADDE); in MipsSETargetLowering()
1073 case ISD::ADDE: in PerformDAGCombine()
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| /external/pcre/dist/sljit/ |
| D | sljitNativePPC_32.c | 124 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2))); in emit_single_op()
127 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
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| D | sljitNativePPC_64.c | 245 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2))); in emit_single_op()
249 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
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| D | sljitNativePPC_common.c | 134 #define ADDE (HI(31) | LO(138)) macro
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator
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| D | SelectionDAG.h | 1099 case ISD::ADDE:
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
213 setOperationAction(ISD::ADDE, MVT::Other, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 71 ADDE, // Add using carry enumerator
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| D | ARMISelLowering.cpp | 742 setOperationAction(ISD::ADDE, MVT::i32, Custom); in ARMTargetLowering()
1131 case ARMISD::ADDE: return "ARMISD::ADDE"; in getTargetNodeName()
6620 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
6880 case ISD::ADDE: in LowerOperation()
8528 if (AddeNode->getOpcode() != ISD::ADDE) in AddCombineTo64bitMLAL()
11172 case ARMISD::ADDE: in computeKnownBitsForTargetNode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 226 case ISD::ADDE: return "adde"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1380 case ISD::ADDE: in ExpandIntegerResult()
1450 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps); in ExpandShiftByConstant()
1702 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
1783 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| D | SelectionDAG.cpp | 2384 case ISD::ADDE: { in computeKnownBits()
3837 case ISD::ADDE: in getNode()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 153 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 128 setOperationAction(ISD::ADDE, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1642 setOperationAction(ISD::ADDE, MVT::i8, Expand); in HexagonTargetLowering()
1643 setOperationAction(ISD::ADDE, MVT::i16, Expand); in HexagonTargetLowering()
1644 setOperationAction(ISD::ADDE, MVT::i32, Expand); in HexagonTargetLowering()
1645 setOperationAction(ISD::ADDE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1564 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
2834 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2835 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2968 case ISD::ADDE: in LowerOperation()
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| D | SparcInstrInfo.td | 595 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 388 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 94 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 207 setOperationAction(ISD::ADDE, MVT::i32, Custom); in AArch64TargetLowering()
211 setOperationAction(ISD::ADDE, MVT::i64, Custom); in AArch64TargetLowering()
1744 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
2268 case ISD::ADDE: in LowerOperation()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 76 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SITargetLowering()
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| D | R600ISelLowering.cpp | 186 setOperationAction(ISD::ADDE, VT, Expand); in R600TargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 421 case ISD::ADDE: in IsProfitableToFold()
|