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Searched refs:AFGR64RegClass (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsOptionRecord.h50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
68 const MCRegisterClass *AFGR64RegClass; variable
DMipsRegisterInfo.cpp176 for (RegIter Reg = Mips::AFGR64RegClass.begin(), in getReservedRegs()
177 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) in getReservedRegs()
DMipsSEInstrInfo.cpp138 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
203 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
276 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
DMipsSEFrameLowering.cpp297 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
359 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
439 if (Mips::AFGR64RegClass.contains(Reg)) { in emitPrologue()
DMipsAsmPrinter.cpp259 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize(); in printSavedRegsBitmask()
272 } else if (Mips::AFGR64RegClass.contains(Reg)) { in printSavedRegsBitmask()
DMipsFastISel.cpp339 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()
736 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()
951 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()
975 RC = &Mips::AFGR64RegClass; in selectSelect()
DMipsISelLowering.cpp3407 if (RC == &Mips::AFGR64RegClass) { in parseRegForInlineAsmConstraint()
3461 return std::make_pair(0U, &Mips::AFGR64RegClass); in getRegForInlineAsmConstraint()
DMipsSEISelLowering.cpp110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsOptionRecord.cpp87 AFGR64RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()