| /external/llvm/test/CodeGen/AMDGPU/ |
| D | fp_to_uint.ll | 46 ; EG-DAG: AND_INT
49 ; EG-DAG: AND_INT
51 ; EG-DAG: AND_INT
76 ; EG-DAG: AND_INT
79 ; EG-DAG: AND_INT
81 ; EG-DAG: AND_INT
97 ; EG-DAG: AND_INT
100 ; EG-DAG: AND_INT
102 ; EG-DAG: AND_INT
127 ; EG-DAG: AND_INT
[all …]
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| D | fp_to_sint.ll | 55 ; EG-DAG: AND_INT
58 ; EG-DAG: AND_INT
60 ; EG-DAG: AND_INT
87 ; EG-DAG: AND_INT
90 ; EG-DAG: AND_INT
92 ; EG-DAG: AND_INT
108 ; EG-DAG: AND_INT
111 ; EG-DAG: AND_INT
113 ; EG-DAG: AND_INT
138 ; EG-DAG: AND_INT
[all …]
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| D | setcc-equivalent.ll | 4 ; EG: AND_INT
16 ; EG: AND_INT
17 ; EG: AND_INT
19 ; EG: AND_INT
21 ; EG: AND_INT
|
| D | udivrem.ll | 20 ; EG: AND_INT
77 ; EG-DAG: AND_INT
100 ; EG-DAG: AND_INT
181 ; EG-DAG: AND_INT
204 ; EG-DAG: AND_INT
227 ; EG-DAG: AND_INT
250 ; EG-DAG: AND_INT
|
| D | load-i1.ll | 12 ; EG: AND_INT
26 ; EG: AND_INT
41 ; EG: AND_INT
|
| D | parallelandifcollapse.ll | 7 ; CHECK: AND_INT
8 ; CHECK-NEXT: AND_INT
|
| D | and.ll | 8 ; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
9 ; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
24 ; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
25 ; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
26 ; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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| D | store.ll | 23 ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
25 ; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
55 ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
59 ; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
|
| D | setcc.ll | 95 ; R600-DAG: AND_INT
97 ; R600-DAG: AND_INT
113 ; R600-DAG: AND_INT
|
| D | setcc-opt.ll | 13 ; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1
30 ; EG: AND_INT T{{[0-9]+.[XYZW]}}, PS, 1
|
| D | udivrem64.ll | 111 ;EG: AND_INT {{.*}}, 1,
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| D | sdivrem64.ll | 111 ;EG: AND_INT {{.*}}, 1,
|
| D | kernel-args.ll | 7 ; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
44 ; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
| D | llvm.AMDGPU.bfe.u32.ll | 167 ; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1,
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| D | Dops.java | 629 public static final Dop AND_INT = field in Dops
630 new Dop(Opcodes.AND_INT, Opcodes.AND_INT,
758 new Dop(Opcodes.AND_INT_2ADDR, Opcodes.AND_INT,
759 Opcodes.AND_INT, Form12x.THE_ONE, true);
886 new Dop(Opcodes.AND_INT_LIT16, Opcodes.AND_INT,
918 new Dop(Opcodes.AND_INT_LIT8, Opcodes.AND_INT,
1246 set(AND_INT);
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| D | RopToDop.java | 303 MAP.put(Rops.AND_INT, Dops.AND_INT_2ADDR); in MAP.put() argument
|
| /external/dexmaker/src/dx/java/com/android/dx/io/ |
| D | Opcodes.java | 184 public static final int AND_INT = 0x95; field in Opcodes
|
| D | OpcodeInfo.java | 622 public static final Info AND_INT = field in OpcodeInfo
623 new Info(Opcodes.AND_INT, "and-int",
1245 set(AND_INT);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 360 def AND_INT : R600_2OP <
361 0x30, "AND_INT",
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| D | Rops.java | 314 public static final Rop AND_INT = field in Rops
1528 AND_INT, AND_LONG, null, null); in opAnd()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 778 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| D | MethodAnalyzer.java | 869 case AND_INT:
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/ |
| D | Opcode.java | 184 …AND_INT(0x95, "and-int", ReferenceType.NONE, Format.Format23x, Opcode.CAN_CONTINUE | Opcode.SETS_R… enumConstant
|