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Searched refs:AddrIdx (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp116 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument
122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange()
149 unsigned AddrIdx; in EmitInstruction() local
151 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction()
156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction()
162 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction()
202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument
223 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
234 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess()
242 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
DMipsMCNaCl.h20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
/external/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp175 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr); in findMatchingDSInst() local
176 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx); in findMatchingDSInst()
177 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx); in findMatchingDSInst()
/external/llvm/lib/Target/Mips/
DMipsDelaySlotFiller.cpp689 unsigned AddrIdx; in searchRange() local
690 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) && in searchRange()
691 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) || in searchRange()