Home
last modified time | relevance | path

Searched refs:ArgFlags (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/CodeGen/
DCallingConvLower.cpp47 ISD::ArgFlagsTy ArgFlags) { in HandleByVal() argument
48 unsigned Align = ArgFlags.getByValAlign(); in HandleByVal()
49 unsigned Size = ArgFlags.getByValSize(); in HandleByVal()
76 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; in AnalyzeFormalArguments() local
77 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeFormalArguments()
94 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in CheckReturn() local
95 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
108 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in AnalyzeReturn() local
109 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeReturn()
126 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in AnalyzeCallOperands() local
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.h45 MVT LocVT, ISD::ArgFlagsTy &ArgFlags, in finishStackBlock() argument
50 unsigned Align = std::min(ArgFlags.getOrigAlign(), StackAlign); in finishStackBlock()
67 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_AArch64_Custom_Stack_Block() argument
75 if (!ArgFlags.isInConsecutiveRegsLast()) in CC_AArch64_Custom_Stack_Block()
78 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8); in CC_AArch64_Custom_Stack_Block()
86 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_AArch64_Custom_Block() argument
112 if (!ArgFlags.isInConsecutiveRegsLast()) in CC_AArch64_Custom_Block()
134 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign); in CC_AArch64_Custom_Block()
DAArch64CallingConvention.td16 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
DAArch64ISelLowering.cpp2905 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in LowerCall() local
2908 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); in LowerCall()
2927 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in LowerCall() local
2935 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo); in LowerCall()
/external/llvm/lib/Target/ARM/
DARMCallingConv.h60 ISD::ArgFlagsTy &ArgFlags, in CC_ARM_APCS_Custom_f64() argument
114 ISD::ArgFlagsTy &ArgFlags, in CC_ARM_AAPCS_Custom_f64() argument
146 ISD::ArgFlagsTy &ArgFlags, in RetCC_ARM_APCS_Custom_f64() argument
157 ISD::ArgFlagsTy &ArgFlags, in RetCC_ARM_AAPCS_Custom_f64() argument
159 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, in RetCC_ARM_AAPCS_Custom_f64()
182 ISD::ArgFlagsTy &ArgFlags, in CC_ARM_AAPCS_Custom_Aggregate() argument
195 ArgFlags.getOrigAlign())); in CC_ARM_AAPCS_Custom_Aggregate()
197 if (!ArgFlags.isInConsecutiveRegsLast()) in CC_ARM_AAPCS_Custom_Aggregate()
DARMFastISel.cpp200 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1880 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, in ProcessCallArgs() argument
1887 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, in ProcessCallArgs()
2211 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; in ARMEmitLibcall() local
2215 ArgFlags.reserve(I->getNumOperands()); in ARMEmitLibcall()
2232 ArgFlags.push_back(Flags); in ARMEmitLibcall()
2238 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2322 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; in SelectCall() local
2327 ArgFlags.reserve(arg_size); in SelectCall()
2365 ArgFlags.push_back(Flags); in SelectCall()
[all …]
DARMCallingConv.td14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
121 CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8",
/external/llvm/lib/Target/X86/
DX86CallingConv.h26 ISD::ArgFlagsTy &ArgFlags, in CC_X86_32_VectorCallIndirect() argument
31 ArgFlags.setInReg(); in CC_X86_32_VectorCallIndirect()
/external/clang/include/clang/Basic/
DIdentifierTable.h621 ArgFlags = ZeroArg|OneArg enumerator
627 assert((InfoPtr & ArgFlags) == 0 &&"Insufficiently aligned IdentifierInfo"); in Selector()
633 assert((InfoPtr & ArgFlags) == 0 &&"Insufficiently aligned IdentifierInfo"); in Selector()
639 return reinterpret_cast<IdentifierInfo *>(InfoPtr & ~ArgFlags); in getAsIdentifierInfo()
643 return reinterpret_cast<MultiKeywordSelector *>(InfoPtr & ~ArgFlags); in getMultiKeywordSelector()
647 return InfoPtr & ArgFlags; in getIdentifierInfoFlag()
/external/llvm/include/llvm/Target/
DTargetCallingConv.td42 class CCIfByVal<CCAction A> : CCIf<"ArgFlags.isByVal()", A> {
47 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
56 class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
60 class CCIfNest<CCAction A> : CCIf<"ArgFlags.isNest()", A> {}
64 class CCIfSplit<CCAction A> : CCIf<"ArgFlags.isSplit()", A> {}
68 class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {}
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp107 ISD::ArgFlagsTy ArgFlags, CCState &State);
112 ISD::ArgFlagsTy ArgFlags, CCState &State);
117 ISD::ArgFlagsTy ArgFlags, CCState &State);
122 ISD::ArgFlagsTy ArgFlags, CCState &State);
127 ISD::ArgFlagsTy ArgFlags, CCState &State);
132 ISD::ArgFlagsTy ArgFlags, CCState &State);
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
147 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon_VarArg() argument
152 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State); in CC_Hexagon_VarArg()
[all …]
/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h177 ISD::ArgFlagsTy ArgFlags, CCState &State);
184 ISD::ArgFlagsTy &ArgFlags, CCState &State);
443 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
/external/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h886 ISD::ArgFlagsTy &ArgFlags,
892 ISD::ArgFlagsTy &ArgFlags,
898 ISD::ArgFlagsTy &ArgFlags,
DPPCFastISel.cpp182 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1268 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, in processCallArgs() argument
1280 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS); in processCallArgs()
1499 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; in fastLowerCall() local
1504 ArgFlags.reserve(NumArgs); in fastLowerCall()
1530 ArgFlags.push_back(Flags); in fastLowerCall()
1537 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
DPPCISelLowering.cpp2568 ISD::ArgFlagsTy &ArgFlags, in CC_PPC32_SVR4_Custom_Dummy() argument
2576 ISD::ArgFlagsTy &ArgFlags, in CC_PPC32_SVR4_Custom_AlignArgRegs() argument
2603 ISD::ArgFlagsTy &ArgFlags, in CC_PPC32_SVR4_Custom_AlignFPArgRegs() argument
4552 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in LowerCall_32SVR4() local
4556 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, in LowerCall_32SVR4()
4560 ArgFlags, CCInfo); in LowerCall_32SVR4()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
DAMDGPUISelLowering.cpp36 ISD::ArgFlagsTy ArgFlags, CCState &State) { in allocateStack() argument
38 ArgFlags.getOrigAlign()); in allocateStack()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp301 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; in AnalyzeArguments() local
308 if (ArgFlags.isSExt()) in AnalyzeArguments()
310 else if (ArgFlags.isZExt()) in AnalyzeArguments()
317 if (ArgFlags.isByVal()) { in AnalyzeArguments()
318 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); in AnalyzeArguments()
339 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); in AnalyzeArguments()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2370 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, in CC_MipsO32() argument
2379 if (ArgFlags.isByVal()) in CC_MipsO32()
2383 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { in CC_MipsO32()
2386 if (ArgFlags.isSExt()) in CC_MipsO32()
2388 else if (ArgFlags.isZExt()) in CC_MipsO32()
2398 if (ArgFlags.isSExt()) in CC_MipsO32()
2400 else if (ArgFlags.isZExt()) in CC_MipsO32()
2413 unsigned OrigAlign = ArgFlags.getOrigAlign(); in CC_MipsO32()
2460 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_MipsO32_FP32() argument
2463 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); in CC_MipsO32_FP32()
[all …]
DMipsFastISel.cpp211 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
216 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_MipsO32_FP32() argument
222 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_MipsO32_FP64() argument
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp41 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet() argument
43 assert (ArgFlags.isSRet()); in CC_Sparc_Assign_SRet()
54 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64() argument
82 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64() argument
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full() argument
151 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half() argument