Searched refs:ArgRegs (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 198 SmallVectorImpl<unsigned> &ArgRegs,
1878 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument
1945 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2209 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local
2213 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2230 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2238 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2320 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local
2325 ArgRegs.reserve(arg_size); in SelectCall()
2363 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 180 SmallVectorImpl<unsigned> &ArgRegs,
1266 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument
1323 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1497 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local
1502 ArgRegs.reserve(NumArgs); in fastLowerCall()
1528 ArgRegs.push_back(Arg); in fastLowerCall()
1537 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| D | PPCISelLowering.cpp | 2578 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
2582 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2584 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2591 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2605 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
2610 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2612 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2616 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2617 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1375 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1379 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1380 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1384 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1394 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3706 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
3718 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3768 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3792 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local
3793 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
3804 if (ArgRegs.size() == Idx) in writeVarArgRegs()
3810 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
3822 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
3824 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 549 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
552 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
553 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2880 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local
2925 ArgRegs.push_back(ResultReg); in fastLowerCall()
2957 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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