Searched refs:BITFIELD64_RANGE (Results 1 – 5 of 5) sorted by relevance
| /external/mesa3d/src/mesa/swrast_setup/ |
| D | ss_context.c | 146 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) in setup_vertex_format()
157 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_GENERIC0, _TNL_NUM_GENERIC)) { in setup_vertex_format()
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| /external/mesa3d/src/mesa/main/ |
| D | mtypes.h | 63 #define BITFIELD64_RANGE(b, count) \ macro
191 #define VERT_BIT_ALL BITFIELD64_RANGE(0, VERT_ATTRIB_MAX)
194 #define VERT_BIT_FF_ALL BITFIELD64_RANGE(0, VERT_ATTRIB_FF_MAX)
197 BITFIELD64_RANGE(VERT_ATTRIB_TEX(0), VERT_ATTRIB_TEX_MAX)
199 BITFIELD64_RANGE(VERT_ATTRIB_POS, VERT_ATTRIB_TEX(VERT_ATTRIB_TEX_MAX))
203 BITFIELD64_RANGE(VERT_ATTRIB_GENERIC_NV(0), VERT_ATTRIB_GENERIC_NV_MAX)
207 BITFIELD64_RANGE(VERT_ATTRIB_GENERIC(0), VERT_ATTRIB_GENERIC_MAX)
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_swtcl.c | 104 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) ) { in r200SetVertexFormat()
164 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in r200SetVertexFormat()
256 if ((0 == (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) in r200ChooseVertexState()
261 if (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in r200ChooseVertexState()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_swtcl.c | 115 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) { in radeonSetVertexFormat()
178 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in radeonSetVertexFormat()
293 (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX) in radeonChooseVertexState()
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | i830_vtbl.c | 96 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in i830_render_start()
127 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in i830_render_start()
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