| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 205 #define BITS5(_b4,_b3,_b2,_b1,_b0) \ macro
2404 if (INSN(28,24) == BITS5(1,0,0,0,1)) { in dis_ARM64_data_processing_immediate()
2460 if (INSN(28,24) == BITS5(1,0,0,0,0)) { in dis_ARM64_data_processing_immediate()
2807 if (INSN(28,24) == BITS5(0,1,0,1,1) && INSN(21,21) == 0) { in dis_ARM64_data_processing_register()
2916 if (INSN(28,24) == BITS5(0,1,0,1,0)) { in dis_ARM64_data_processing_register()
3445 && INSN(15,11) == BITS5(0,0,0,0,1)) { in dis_ARM64_data_processing_register()
5248 if (INSN(29,25) == BITS5(1,0,1,1,0)) { in dis_ARM64_load_store()
5704 mm == BITS5(1,1,1,1,1) ? mkU64(xferSzB) in dis_ARM64_load_store()
5842 if (mm == BITS5(1,1,1,1,1)) in dis_ARM64_load_store()
5915 mm == BITS5(1,1,1,1,1) ? mkU64(xferSzB) in dis_ARM64_load_store()
[all …]
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| D | guest_arm_toIR.c | 252 #define BITS5(_b4,_b3,_b2,_b1,_b0) \ macro
18809 case BITS5(0,0,1,1,0): in disInstr_THUMB_WRK()
18810 case BITS5(0,0,1,1,1): { in disInstr_THUMB_WRK()
18828 case BITS5(1,0,1,0,0): { in disInstr_THUMB_WRK()
18842 case BITS5(1,0,1,0,1): { in disInstr_THUMB_WRK()
18852 case BITS5(0,0,1,0,1): { in disInstr_THUMB_WRK()
18866 case BITS5(0,0,1,0,0): { in disInstr_THUMB_WRK()
18883 case BITS5(0,1,0,0,1): { in disInstr_THUMB_WRK()
18903 case BITS5(0,1,1,0,0): /* STR */ in disInstr_THUMB_WRK()
18904 case BITS5(0,1,1,0,1): { /* LDR */ in disInstr_THUMB_WRK()
[all …]
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| D | guest_ppc_toIR.c | 9678 #define BITS5(_b4,_b3,_b2,_b1,_b0) \ macro
9792 mkU32( BITS5(1,0,1,1,1) ) ) ) ); in Get_lmd()
9796 mkU32( BITS5(1,1,0,0,0) ) ) ) ); in Get_lmd()
9800 mkU32( BITS5(1,1,0,1,0) ) ) ) ); in Get_lmd()
9804 mkU32( BITS5(1,1,1,0,0) ) ) ) ); in Get_lmd()
9808 mkU32( BITS5(1,1,0,0,1) ) ) ) ); in Get_lmd()
9812 mkU32( BITS5(1,1,0,1,1) ) ) ) ); in Get_lmd()
9816 mkU32( BITS5(1,1,1,0,1) ) ) ) ); in Get_lmd()
10281 #undef BITS5
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| D | guest_mips_toIR.c | 452 #define BITS5(_b4,_b3,_b2,_b1,_b0) \ macro
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