Searched refs:CTX_PP_CNTL (Results 1 – 10 of 10) sorted by relevance
341 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE | in r200UpdateFSRouting()351 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ? in r200UpdateFSRouting()355 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE; in r200UpdateFSRouting()356 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ? in r200UpdateFSRouting()388 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()407 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()469 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()496 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()
1003 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_BLEND_ENABLE_MASK | R200_MULTI_PASS_ENABLE); in r200UpdateAllTexEnv()1004 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= rmesa->state.envneeded << R200_TEX_BLEND_0_ENABLE_SHIFT; in r200UpdateAllTexEnv()1047 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_0_ENABLE << unit); in disable_tex_obj_state()1518 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; in r200_validate_texture()1613 if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_ENABLE_MASK) == R200_TEX_0_ENABLE && in r200UpdateTextureState()1618 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE; in r200UpdateTextureState()1624 if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) && in r200UpdateTextureState()1639 if (!(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE)) in r200UpdateTextureState()
761 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; in r200UpdateSpecular()810 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { in r200UpdateSpecular()812 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; in r200UpdateSpecular()1737 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ALPHA_TEST_ENABLE; in r200Enable()1739 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ALPHA_TEST_ENABLE; in r200Enable()1797 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_FOG_ENABLE; in r200Enable()1800 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_FOG_ENABLE; in r200Enable()1848 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_LINE; in r200Enable()1850 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_LINE; in r200Enable()1928 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_POLY; in r200Enable()[all …]
107 #define CTX_PP_CNTL 9 macro
504 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); in ctx_emit_cs()958 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE in r200InitState()
563 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; in radeonUpdateSpecular()626 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { in radeonUpdateSpecular()628 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; in radeonUpdateSpecular()1519 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ALPHA_TEST_ENABLE; in radeonEnable()1521 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ALPHA_TEST_ENABLE; in radeonEnable()1605 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE; in radeonEnable()1608 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE; in radeonEnable()1654 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_LINE; in radeonEnable()1656 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_LINE; in radeonEnable()1663 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_PATTERN_ENABLE; in radeonEnable()[all …]
105 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); in radeonEmitScissor()116 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
98 #define CTX_PP_CNTL 9 macro
1073 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= in radeon_validate_texture()1134 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK)); in radeonUpdateTextureState()
386 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); in ctx_emit_cs()700 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | in radeonInitState()