| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 841 enum CondCode { enum
874 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
880 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
887 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
895 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
901 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
905 CondCode getSetCCSwappedOperands(CondCode Operation);
911 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
917 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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| D | Analysis.h | 87 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
91 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
96 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionOptimizer.cpp | 96 typedef std::tuple<int, unsigned, AArch64CC::CondCode> CmpInfo;
102 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
104 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
211 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { in getAdjustedCmp()
225 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp()
256 AArch64CC::CondCode Cmp; in modifyCmp()
287 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
291 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
301 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm) in adjustTo()
355 AArch64CC::CondCode HeadCmp; in runOnMachineFunction()
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| D | AArch64ConditionalCompares.cpp | 165 AArch64CC::CondCode HeadCmpBBCC;
171 AArch64CC::CondCode CmpBBTailCC;
272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
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| D | AArch64ISelLowering.cpp | 985 unsigned CondCode = MI->getOperand(3).getImm(); in EmitF128CSEL() local
998 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); in EmitF128CSEL()
1050 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { in changeIntCCToAArch64CC()
1078 static void changeFPCCToAArch64CC(ISD::CondCode CC, in changeFPCCToAArch64CC()
1079 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC() argument
1080 AArch64CC::CondCode &CondCode2) { in changeFPCCToAArch64CC()
1087 CondCode = AArch64CC::EQ; in changeFPCCToAArch64CC()
1091 CondCode = AArch64CC::GT; in changeFPCCToAArch64CC()
1095 CondCode = AArch64CC::GE; in changeFPCCToAArch64CC()
1098 CondCode = AArch64CC::MI; in changeFPCCToAArch64CC()
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| D | AArch64BranchRelaxation.cpp | 356 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm(); in invertBccCondition()
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| D | AArch64InstrInfo.cpp | 183 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in ReverseBranchCondition()
409 AArch64CC::CondCode CC; in insertSelect()
414 CC = AArch64CC::CondCode(Cond[0].getImm()); in insertSelect()
929 AArch64CC::CondCode CC; in optimizeCompareInstr()
934 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm(); in optimizeCompareInstr()
946 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
2968 AArch64CC::CondCode CC = in optimizeCondBranch()
2969 (AArch64CC::CondCode)DefMI->getOperand(3).getImm(); in optimizeCondBranch()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 38 enum CondCode { enum
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
216 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
238 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
301 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
409 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc) in reverseCondCode()
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); in reverseCondCode()
33 static inline CondCode inverseCondCode(CondCode cc) in inverseCondCode()
35 return static_cast<CondCode>(cc ^ 7); in inverseCondCode()
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| D | nv50_ir.h | 168 enum CondCode enum
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; } in setCondition()
827 CondCode getCondition() const { return setCond; } in getCondition()
830 CondCode setCond;
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| D | nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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| D | nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, in mkCmp()
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred) in mkFlow()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 33 enum CondCode { enum
64 unsigned GetCondBranchFromCond(CondCode CC);
68 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
72 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
76 CondCode getCondFromCMovOpc(unsigned Opc);
80 CondCode GetOppositeBranchCondition(CondCode CC);
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.h | 33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
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| D | MipsInstPrinter.cpp | 37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
264 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 578 class CondCode; // ISD::CondCode enums
579 def SETOEQ : CondCode; def SETOGT : CondCode;
580 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
581 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
582 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
583 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
585 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
586 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
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| D | TargetLowering.h | 673 getCondCodeAction(ISD::CondCode CC, MVT VT) const { in getCondCodeAction()
686 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { in isCondCodeLegal()
1368 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1741 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1747 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
1945 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2097 ISD::CondCode &CCCode, SDLoc DL) const;
2210 ISD::CondCode Cond, bool foldBooleans,
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
214 inline static const char *getCondCodeName(CondCode Code) { in getCondCodeName()
236 inline static CondCode getInvertedCondCode(CondCode Code) { in getInvertedCondCode()
239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in getNZCVToSatisfyCondCode()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFormats.td | 64 multiclass ComparisonInt<CondCode cond, string name> {
72 multiclass ComparisonFP<CondCode cond, string name> {
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 163 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
185 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
200 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 177 const ISD::CondCode Cond; in ARMTargetLowering()
262 const ISD::CondCode Cond; in ARMTargetLowering()
361 const ISD::CondCode Cond; in ARMTargetLowering()
1312 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { in IntCCToARMCC()
1329 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC() argument
1335 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
1337 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
1339 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
1340 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
1341 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 464 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { in NegateCC()
480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
497 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 58 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
201 AArch64CC::CondCode Code;
255 struct CondCodeOp CondCode; member
287 CondCode = o.CondCode; in AArch64Operand()
352 AArch64CC::CondCode getCondCode() const { in getCondCode()
354 return CondCode.Code; in getCondCode()
1693 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateCondCode()
1695 Op->CondCode.Code = Code; in CreateCondCode()
2349 AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) { in parseCondCodeString()
2350 AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower()) in parseCondCodeString()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.h | 192 unsigned CondCode = 0) const;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1149 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1150 ISD::CondCode InverseCC = in LowerSELECT_CC()
1157 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC); in LowerSELECT_CC()
1184 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1186 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
1192 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); in LowerSELECT_CC()
1204 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1973 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1985 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()
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