Home
last modified time | relevance | path

Searched refs:CreateReg (Results 1 – 25 of 45) sorted by relevance

12

/external/llvm/lib/Target/X86/
DX86InstrBuilder.h65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, in getFullAddress()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
81 MO.push_back(MachineOperand::CreateReg(0, false, false, in getFullAddress()
/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp115 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
159 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
199 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
235 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
DHexagonPeephole.cpp223 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
230 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first, in runOnMachineFunction()
DHexagonHardwareLoops.cpp1870 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true)); in createPreheaderForLoop()
1881 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
1896 PN->addOperand(MachineOperand::CreateReg(NewPR, false)); in createPreheaderForLoop()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp69 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK, in ImposeStackInputOrdering()
82 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK, in ImposeStackOrdering()
/external/llvm/lib/Target/PowerPC/
DPPCTOCRegDeps.cpp122 MI.addOperand(MachineOperand::CreateReg(PPC::X2, in processBlock()
DPPCInstrInfo.cpp501 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
512 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
570 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
584 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
1755 MachineOperand::CreateReg(*ImpDefs, true, true)); in optimizeCompareInstr()
1761 MachineOperand::CreateReg(*ImpUses, false, true)); in optimizeCompareInstr()
/external/llvm/lib/CodeGen/
DLiveVariables.cpp247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
DExpandPostRAPseudos.cpp76 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true)); in TransferImplicitDefs()
DMachineInstr.cpp636 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); in addImplicitDefUseOperands()
640 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); in addImplicitDefUseOperands()
1856 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
1922 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
1959 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp200 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
229 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
DThumb2InstrInfo.cpp490 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
521 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUMCInstLower.cpp51 MCOp = MCOperand::CreateReg(MO.getReg()); in lower()
DR600InstrInfo.cpp218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in AnalyzeBranch()
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in AnalyzeBranch()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp596 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in addStackMapLiveVars()
644 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true)); in selectPatchpoint()
807 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
826 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
832 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true, in selectPatchpoint()
1129 Op = MachineOperand::CreateReg(Reg, false); in selectIntrinsicCall()
1145 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address), in selectIntrinsicCall()
DFunctionLoweringInfo.cpp346 unsigned FunctionLoweringInfo::CreateReg(MVT VT) { in CreateReg() function in FunctionLoweringInfo
371 unsigned R = CreateReg(RegisterVT); in CreateRegs()
/external/llvm/include/llvm/CodeGen/
DFunctionLoweringInfo.h164 unsigned CreateReg(MVT VT);
DMachineInstrBuilder.h69 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
DMachineOperand.h597 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp192 return MachineOperand::CreateReg(Orig.getReg(), in copyRegOperandAsImplicit()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1640 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() function in __anon26fd99540211::AArch64Operand
2849 AArch64Operand::CreateReg(Reg, true, S, getLoc(), getContext())); in tryParseVectorRegister()
2898 AArch64Operand::CreateReg(Reg, false, S, getLoc(), getContext())); in parseRegister()
3125 AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); in tryParseGPR64sp0Operand()
3146 AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); in tryParseGPR64sp0Operand()
3858 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
3996 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), in MatchAndEmitInstruction()
4011 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), in MatchAndEmitInstruction()
4027 Operands[1] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), in MatchAndEmitInstruction()
4043 Operands[2] = AArch64Operand::CreateReg(zreg, false, Op.getStartLoc(), in MatchAndEmitInstruction()
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp1631 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true, in ParseIntelOffsetOfOperator()
1769 return X86Operand::CreateReg(RegNo, Start, End); in ParseIntelOperand()
1799 return X86Operand::CreateReg(RegNo, Start, End); in ParseATTOperand()
2258 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); in ParseInstruction()
2270 Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); in ParseInstruction()
2278 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), in ParseInstruction()
2288 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); in ParseInstruction()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp329 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anoncba7d3b40111::SparcOperand
743 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
804 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp582 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function
1146 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); in parseOperand()
1162 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); in parseOperand()
1172 Operands.push_back(HexagonOperand::CreateReg( in parseOperand()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp642 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, in CreateReg() function in __anond0efcad40311::MipsOperand
1162 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser); in createNumericReg()
1170 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser); in createGPRReg()
1178 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser); in createFGRReg()
1186 return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser); in createHWRegsReg()
1194 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser); in createFCCReg()
1202 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser); in createACCReg()
1210 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser); in createMSA128Reg()
1218 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser); in createMSACtrlReg()

12