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Searched refs:DAGCombiner (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dshuffle-combine-crash.ll3 ; Verify that DAGCombiner does not crash when checking if it is
7 ; The DAGCombiner avoids folding shuffles if
11 ; Before, the DAGCombiner forgot to check if the resulting shuffle
Dshift-combine-crash.ll3 ; Verify that DAGCombiner doesn't crash with an assertion failure in the
9 ; DAGCombiner will then try to simplify the vector shift and check if the
19 ; Also, verify that DAGCombiner doesn't crash when trying to combine shifts
Ddag-merge-fast-accesses.ll5 ; Verify that the DAGCombiner is creating unaligned 16-byte loads and stores
57 ;; ..but is not currently. See the UseAA FIXME in DAGCombiner.cpp
Dwide-integer-fold.ll4 ; DAGCombiner should fold this to a simple constant.
Dand-load-fold.ll3 ; Verify that the DAGCombiner doesn't wrongly remove the 'and' from the dag.
Dsimple-zext.ll3 ; A bug in DAGCombiner prevented it forming a zextload in this simple case
Dcvtv2f32.ll1 ; A bug fix in the DAGCombiner made this test fail, so marking as xfail
Dvbinop-simplify-bug.ll4 ; DAGCombiner::SimplifyVBinOp in an attempt to refactor some code
Ddagcombine-shifts.ll7 ; This will help DAGCombiner to identify and then fold the sequence
183 ; Make sure that the combined dags are legal if we run the DAGCombiner after
Dnarrow-shl-load.ll6 ; DAGCombiner should fold this code in finite time.
Dshl_undef.ll5 ; DAGCombiner optimization pass. These are changed to undef and in turn
Dbuildvec-insertvec.ll20 ; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a
Dfold-vector-sext-crash2.ll4 ; DAGCombiner crashes during sext folding
Dinsertps-O0-bug.ll30 ; arguments needed by the entry block. This is enough to enable the DAGCombiner
/external/llvm/test/CodeGen/PowerPC/
Ddelete-node.ll3 ; The DAGCombiner leaves behind a dead node in this testcase. Currently
5 ; DAGCombiner to be able to eliminate the dead node.
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp86 class DAGCombiner { class
461 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) in DAGCombiner() function in __anonbfbf49f20111::DAGCombiner
502 DAGCombiner &DC;
504 explicit WorklistRemover(DAGCombiner &dc) in WorklistRemover()
518 ((DAGCombiner*)DC)->AddToWorklist(N); in AddToWorklist()
522 ((DAGCombiner*)DC)->removeFromWorklist(N); in RemoveFromWorklist()
527 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); in CombineTo()
532 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); in CombineTo()
538 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); in CombineTo()
543 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); in CommitTargetLoweringOpt()
[all …]
DCMakeLists.txt2 DAGCombiner.cpp
DAndroid.mk4 DAGCombiner.cpp \
/external/llvm/test/CodeGen/AArch64/
Darm64-shrink-v1i64.ll3 ; The DAGCombiner tries to do following shrink:
Darm64-dagcombiner-convergence.ll3 ; DAGCombiner should converge.
Dneon-or-combine.ll3 ; Check that the DAGCombiner does not crash with an assertion failure
/external/llvm/test/CodeGen/WebAssembly/
Dcopysign-casts.ll3 ; DAGCombiner oddly folds casts into the rhs of copysign. Test that they get
/external/llvm/test/CodeGen/AMDGPU/
Ddagcombiner-bug-illegal-vec4-int-to-fp.ll4 ; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
Dfneg.f64.ll37 ; DAGCombiner will transform:
Dfneg.ll43 ; DAGCombiner will transform:

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