Searched refs:Def1 (Results 1 – 7 of 7) sorted by relevance
| /external/clang/test/SemaTemplate/ |
| D | instantiation-default-1.cpp | 2 template<typename T, typename U = const T> struct Def1;
4 template<> struct Def1<int> { struct
8 template<> struct Def1<const int> { // expected-note{{previous definition is here}} struct
12 template<> struct Def1<int&> { struct
16 void test_Def1(Def1<int, const int> *d1, Def1<const int, const int> *d2, in test_Def1()
17 Def1<int&, int&> *d3) { in test_Def1()
39 template<> struct Def1<const int, const int> { }; // expected-error{{redefinition of 'Def1<const in… struct
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenMux.cpp | 71 MachineInstr *Def1, *Def2; member
75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1), in MuxInfo()
261 MachineInstr *Def1 = It1, *Def2 = It2; in genMuxInBlock() local
262 MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2); in genMuxInBlock()
284 MachineBasicBlock::iterator At = CanDown ? Def2 : Def1; in genMuxInBlock()
285 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); in genMuxInBlock()
299 B.erase(MX.Def1); in genMuxInBlock()
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| D | HexagonEarlyIfConv.cpp | 446 MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg()); in computePhiCost() local
448 if (!TII->isPredicable(Def1) || !TII->isPredicable(Def3)) in computePhiCost()
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| /external/clang/test/Modules/Inputs/merge-class-definition-visibility/ |
| D | modmap | 1 module Def1 {
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| /external/markdown/tests/extensions-x-def_list/ |
| D | simple_def-lists.txt | 4 : Def1
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1517 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
1520 if (!produceSameValue(Def0, Def1, MRI)) in produceSameValue()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 4045 bool Def1 = (Elems[I1].getOpcode() != ISD::UNDEF); in buildVector() local
4047 if (Def1 || Def2) { in buildVector()
4048 SDValue Elem1 = Elems[Def1 ? I1 : I2]; in buildVector()
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