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Searched refs:DoubleRegs (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td101 def : Pat<(i64 (selectcc DoubleRegs:$lhs, DoubleRegs:$rhs, DoubleRegs:$tval,
102 DoubleRegs:$fval, SETGT)),
103 (COMBINE_rr (MUX_rr (CMPGT64rr DoubleRegs:$lhs, DoubleRegs:$rhs),
104 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
105 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
106 (MUX_rr (CMPGT64rr DoubleRegs:$lhs, DoubleRegs:$rhs),
107 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
108 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
112 def : Pat<(i64 (selectcc DoubleRegs:$lhs, DoubleRegs:$rhs, DoubleRegs:$tval,
113 DoubleRegs:$fval, SETLT)),
[all …]
DHexagonIntrinsicsDerived.td14 def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
22 (M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
24 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
27 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
28 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
29 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
30 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
35 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
36 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
DHexagonInstrInfoV3.td102 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
103 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
104 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
105 (i64 DoubleRegs:$Rt))))],
111 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
136 defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
195 MInst<(outs DoubleRegs:$Rdd),
196 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
218 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
224 MInst <(outs DoubleRegs:$Rxx),
[all …]
DHexagonInstrInfoVector.td19 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
20 def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
21 def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
32 def : Pat <(b (bitconvert (a DoubleRegs:$src))),
33 (b DoubleRegs:$src)>;
34 def : Pat <(a (bitconvert (b DoubleRegs:$src))),
35 (a DoubleRegs:$src)>;
104 [(set (v4i16 DoubleRegs:$dst),
105 (Op (v4i16 DoubleRegs:$src1), u4ImmPred:$src2))]> {
112 [(set (v2i32 DoubleRegs:$dst),
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DHexagonInstrInfo.td24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
332 [(set (i64 DoubleRegs:$Rdd),
562 : ALU32_rr <(outs DoubleRegs:$dst),
563 (ins PredRegs:$src1, DoubleRegs:$src2),
573 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
574 (ins DoubleRegs:$src),
643 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
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DHexagonInstrAlias.td28 (S2_storerdgp u16_3Imm:$addr, DoubleRegs:$Nt)>;
41 (L2_loadrdgp DoubleRegs:$Nt, u16_3Imm:$addr)>;
75 (S2_storerd_io IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
112 (L2_loadrd_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
118 (L2_loadbzw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
124 (L2_loadbsw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
127 (L2_loadalignb_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
130 (L2_loadalignh_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
150 (L2_ploadrdt_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
167 (S2_pstorerdt_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
[all …]
DHexagonIntrinsicsV4.td70 def : Pat <(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),
71 (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>;
83 Pat <(IntID (i64 DoubleRegs:$src1), immPred:$src2),
84 (MI (i64 DoubleRegs:$src1), immPred:$src2)>;
180 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
182 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
186 def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
188 (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
DHexagonIntrinsics.td26 (MI DoubleRegs:$Rs)>;
42 (MI DoubleRegs:$Rs, imm:$It)>;
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
54 (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
94 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
98 (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
102 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
106 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
110 (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
114 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, PredRegs:$Ru)>;
[all …]
DHexagonInstrInfoV5.td57 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
82 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
127 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
259 : T_fcmp <mnemonic, DoubleRegs, MinOp,
291 // DoubleRegs
310 // DoubleRegs
340 // DoubleRegs
375 // DoubleRegs
532 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
551 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
[all …]
DHexagonInstrInfoV4.td296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
432 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
440 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
443 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
458 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
476 DoubleRegs, 0b0100>;
485 DoubleRegs, 0b0010>;
[all …]
DHexagonIsetDx.td17 (outs DoubleRegs:$Rdd),
65 (outs DoubleRegs:$Rdd),
196 (outs DoubleRegs:$Rdd),
289 (outs DoubleRegs:$Rdd),
364 (outs DoubleRegs:$Rdd),
380 (outs DoubleRegs:$Rdd),
454 (outs DoubleRegs:$Rdd),
511 (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt),
DHexagonSplitDouble.cpp216 BitVector DoubleRegs(NumRegs); in partitionRegisters() local
220 DoubleRegs.set(i); in partitionRegisters()
224 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
235 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
274 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
DHexagonInstrInfoV60.td2054 : T_HVX_rol <asmString, DoubleRegs, u6Imm>;
2066 : T_HVX_rol_acc <asmString, DoubleRegs, u6Imm>;
2118 class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>;
2139 def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2),
2140 (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2),
2230 : SInst2<(outs DoubleRegs:$dst),
2231 (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),
DHexagonRegisterInfo.td213 def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
DHexagonOperands.td597 def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp121 static const MCPhysReg DoubleRegs[32] = { variable
373 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
1015 RegNo = DoubleRegs[intVal/2]; in matchRegisterName()