Searched refs:DstR (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 338 const unsigned DstR = MI->getOperand(0).getReg(); in processInstructionForSLM() local
341 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) in processInstructionForSLM()
369 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM()
370 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM()
380 const MachineOperand &SrcR = MI->getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 158 MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
684 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool Cond) { in genTfrFor() argument
698 .addReg(DstR, RegState::Define, DstSR) in genTfrFor()
|
| D | HexagonGenInsert.cpp | 490 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
639 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
641 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm()
|
| D | HexagonSplitDouble.cpp | 978 unsigned DstR = MI->getOperand(0).getReg(); in splitInstr() local
979 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
|