/external/llvm/lib/Target/X86/InstPrinter/ |
D | X86InstComments.cpp | 49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { in getZeroExtensionTypes() argument 59 DstVT = MVT::v8i16; in getZeroExtensionTypes() 64 DstVT = MVT::v16i16; in getZeroExtensionTypes() 71 DstVT = MVT::v4i32; in getZeroExtensionTypes() 76 DstVT = MVT::v8i32; in getZeroExtensionTypes() 83 DstVT = MVT::v2i64; in getZeroExtensionTypes() 88 DstVT = MVT::v4i64; in getZeroExtensionTypes() 96 DstVT = MVT::v4i32; in getZeroExtensionTypes() 101 DstVT = MVT::v8i32; in getZeroExtensionTypes() 108 DstVT = MVT::v2i64; in getZeroExtensionTypes() [all …]
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/external/llvm/lib/Transforms/Scalar/ |
D | Scalarizer.cpp | 488 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); in visitBitCastInst() local 490 if (!DstVT || !SrcVT) in visitBitCastInst() 493 unsigned DstNumElems = DstVT->getNumElements(); in visitBitCastInst() 502 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst() 508 Type *MidTy = VectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst() 534 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
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/external/llvm/lib/Target/X86/ |
D | X86SelectionDAGInfo.cpp | 267 EVT DstVT = Dst.getValueType(); in EmitTargetCodeForMemcpy() local 271 DAG.getNode(ISD::ADD, dl, DstVT, Dst, in EmitTargetCodeForMemcpy() 273 DstVT)), in EmitTargetCodeForMemcpy()
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D | X86FastISel.cpp | 96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 569 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument 572 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend() 1065 EVT DstVT = VA.getValVT(); in X86SelectRet() local 1067 if (SrcVT != DstVT) { in X86SelectRet() 1074 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet() 1084 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet() 1333 EVT DstVT = TLI.getValueType(DL, I->getType()); in X86SelectZExt() local 1334 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt() 1352 if (DstVT == MVT::i64) { in X86SelectZExt() [all …]
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D | X86ISelDAGToDAG.cpp | 596 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local 599 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG() 607 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG() 625 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. in PreprocessISelDAG() 627 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG() 637 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, in PreprocessISelDAG()
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D | X86InstrAVX512.td | 4751 X86VectorVTInfo DstVT, X86MemOperand x86memop, 4754 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst), 4755 (ins DstVT.FRC:$src1, SrcRC:$src), 4759 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst), 4760 (ins DstVT.FRC:$src1, x86memop:$src), 4765 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), 4766 (ins DstVT.RC:$src1, SrcRC:$src2), 4768 [(set DstVT.RC:$dst, 4769 (OpNode (DstVT.VT DstVT.RC:$src1), 4773 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), [all …]
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D | X86ISelLowering.cpp | 12891 MVT DstVT = Op.getSimpleValueType(); in LowerUINT_TO_FP() local 12893 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) && in LowerUINT_TO_FP() 12900 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) in LowerUINT_TO_FP() 12904 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) in LowerUINT_TO_FP() 12968 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, in LowerUINT_TO_FP() 19340 MVT DstVT = Op.getSimpleValueType(); in LowerBITCAST() local 19344 if (DstVT != MVT::f64) in LowerBITCAST() 19372 assert((DstVT == MVT::i64 || in LowerBITCAST() 19373 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && in LowerBITCAST() 19376 if (SrcVT==MVT::i64 && DstVT.isVector()) in LowerBITCAST() [all …]
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D | X86InstrSSE.td | 3964 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag, 3973 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))], 3980 [(set RC:$dst, (DstVT (OpNode RC:$src1, 3988 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>, 3994 ValueType DstVT, ValueType SrcVT, RegisterClass RC, 4004 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>, 4011 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), 6807 ValueType DstVT, ValueType SrcVT, RegisterClass RC, 6817 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>, 6824 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
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/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 987 MVT DstVT; in SelectIToFP() local 989 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP() 992 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP() 1020 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) in SelectIToFP() 1042 if (DstVT == MVT::f32) in SelectIToFP() 1096 MVT DstVT, SrcVT; in SelectFPToI() local 1098 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI() 1101 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI() 1105 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT()) in SelectFPToI() 1137 if (DstVT == MVT::i32) in SelectFPToI() [all …]
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | FastISel.cpp | 1245 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local 1247 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast() 1248 !DstVT.isSimple()) in selectCast() 1253 if (!TLI.isTypeLegal(DstVT)) in selectCast() 1267 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast() 1295 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local 1303 if (SrcVT == DstVT) { in selectBitCast() 1305 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast() 1316 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast() 1631 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local [all …]
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D | LegalizeIntegerTypes.cpp | 2937 EVT DstVT = N->getValueType(0); in ExpandIntOp_SINT_TO_FP() local 2938 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); in ExpandIntOp_SINT_TO_FP() 2941 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first; in ExpandIntOp_SINT_TO_FP() 3042 EVT DstVT = N->getValueType(0); in ExpandIntOp_UINT_TO_FP() local 3048 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); in ExpandIntOp_UINT_TO_FP() 3052 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP() 3102 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr, in ExpandIntOp_UINT_TO_FP() 3105 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); in ExpandIntOp_UINT_TO_FP() 3109 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP() 3112 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first; in ExpandIntOp_UINT_TO_FP()
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D | DAGCombiner.cpp | 5866 EVT DstVT = N->getValueType(0); in CombineExtLoad() local 5896 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() || in CombineExtLoad() 5897 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0))) in CombineExtLoad() 5909 EVT SplitDstVT = DstVT; in CombineExtLoad() 5921 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements(); in CombineExtLoad() 5945 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
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/external/llvm/lib/Target/X86/Utils/ |
D | X86ShuffleDecode.cpp | 431 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT, SmallVectorImpl<int> &Mask) { in DecodeZeroExtendMask() argument 432 unsigned NumDstElts = DstVT.getVectorNumElements(); in DecodeZeroExtendMask() 434 unsigned DstScalarBits = DstVT.getScalarSizeInBits(); in DecodeZeroExtendMask()
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D | X86ShuffleDecode.h | 102 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT,
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.td | 1131 field ValueType DstVT = ArgVT[0]; 1135 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret; 1142 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1); 1625 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, 1627 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]) 1637 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, 1639 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), 1657 [(set P.DstVT:$dst, 1661 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), 1673 [(set P.DstVT:$dst, [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3558 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3560 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3615 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3618 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3623 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3626 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3631 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3633 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3635 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3637 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; [all …]
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D | MipsFastISel.cpp | 1036 MVT DstVT, SrcVT; in selectFPToInt() local 1041 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt() 1044 if (DstVT != MVT::i32) in selectFPToInt()
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D | MipsDSPInstrInfo.td | 1307 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 1309 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 1044 EVT DstVT = N->getValueType(0); in SelectIndexedLoad() local 1067 DstVT = MVT::i32; in SelectIndexedLoad() 1071 if (DstVT == MVT::i64) in SelectIndexedLoad() 1077 InsertTo64 = DstVT == MVT::i64; in SelectIndexedLoad() 1080 DstVT = MVT::i32; in SelectIndexedLoad() 1084 if (DstVT == MVT::i64) in SelectIndexedLoad() 1090 InsertTo64 = DstVT == MVT::i64; in SelectIndexedLoad() 1093 DstVT = MVT::i32; in SelectIndexedLoad() 1112 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in SelectIndexedLoad()
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/external/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 1547 MVT DstVT; in SelectIToFP() local 1549 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP() 1580 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP() 1591 MVT DstVT; in SelectFPToI() local 1593 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI() 1612 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
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D | ARMISelLowering.cpp | 4147 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local 4155 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in CombineVMOVDRRCandidateWithVecOp() 4165 unsigned DstNumElt = DstVT.getVectorNumElements(); in CombineVMOVDRRCandidateWithVecOp() 4180 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp() 4183 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp() 4200 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local 4201 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && in ExpandBITCAST() 4205 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { in ExpandBITCAST() 4215 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST() 4220 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { in ExpandBITCAST()
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/external/llvm/lib/CodeGen/ |
D | CodeGenPrepare.cpp | 776 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local 779 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression() 784 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression() 792 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression() 794 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression() 797 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()
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