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Searched refs:ExitSU (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp215 ExitSU.setInstr(ExitMI); in addSchedBarrierDeps()
228 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); in addSchedBarrierDeps()
230 addVRegUseDeps(&ExitSU, i); in addSchedBarrierDeps()
240 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg)); in addSchedBarrierDeps()
307 if (DefSU == &ExitSU) in addPhysRegDeps()
641 SUnit *ExitSU, unsigned *Depth, in iterateChainSucc() argument
643 if (!SUa || !SUb || SUb == ExitSU) in iterateChainSucc()
677 iterateChainSucc(AA, MFI, DL, SUa, I->getSUnit(), ExitSU, Depth, Visited); in iterateChainSucc()
686 const DataLayout &DL, SUnit *SU, SUnit *ExitSU, in adjustChainDeps() argument
710 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth, in adjustChainDeps()
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DScheduleDAG.cpp41 MRI(mf.getRegInfo()), EntrySU(), ExitSU() { in ScheduleDAG()
53 ExitSU = SUnit(); in clearDAG()
468 if (ExitSU) in InitDAGTopologicalSorting()
469 WorkList.push_back(ExitSU); in InitDAGTopologicalSorting()
639 : SUnits(sunits), ExitSU(exitsu) {} in ScheduleDAGTopologicalSort()
DMachineScheduler.cpp522 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU); in canAddEdge()
526 if (SuccSU != &ExitSU) { in addEdge()
565 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in releaseSucc()
766 ExitSU.biasCriticalPath(); in findRootsAndBiasEdges()
791 releasePredecessors(&ExitSU); in initQueues()
1001 if (!SU->isScheduled && SU != &ExitSU) { in updatePressureDiffs()
1192 if (SU == &ExitSU) in computeCyclicCriticalPath()
1428 SUnit &ExitSU = DAG->ExitSU; in apply() local
1429 MachineInstr *Branch = ExitSU.getInstr(); in apply()
1451 bool Success = DAG->addEdge(&ExitSU, SDep(&SU, SDep::Cluster)); in apply()
[all …]
DPostRASchedulerList.cpp468 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h567 SUnit ExitSU; // Special node for the region exit.
694 SUnit *ExitSU;
716 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
DMachineScheduler.h260 LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), in ScheduleDAGMI()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGVLIW.cpp135 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { in releaseSucc()
DScheduleDAGFast.cpp536 ReleasePredecessors(&ExitSU, CurCycle); in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1501 ReleasePredecessors(&ExitSU); in ListScheduleBottomUp()
/external/llvm/test/CodeGen/X86/
Dmisched-new.ll58 ; Test that the DAG builder can handle an undef vreg on ExitSU.