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Searched refs:ExtType (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h50 struct ExtType { struct
54 ExtType() : Type(0), Width(0) {} in ExtType() function
55 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() argument
58 typedef DenseMap<unsigned, ExtType> RegExtMap;
DHexagonBitTracker.cpp71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1119 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1121 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
DHexagonISelDAGToDAG.cpp380 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
381 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
429 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
/external/llvm/include/llvm/Target/
DTargetLowering.h590 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
595 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
597 return LoadExtActions[ValI][MemI][ExtType]; in getLoadExtAction()
601 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
603 getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
608 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
610 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
611 getLoadExtAction(ExtType, ValVT, MemVT) == Custom); in isLoadExtLegalOrCustom()
1323 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1325 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1042 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1048 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1052 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1054 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1060 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp203 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
500 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
597 switch (ExtType) { in ExpandLoad()
620 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl, in ExpandLoad()
DLegalizeVectorTypes.cpp992 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
1006 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1013 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1039 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1070 ExtType); in SplitVecRes_MLOAD()
1082 ExtType); in SplitVecRes_MLOAD()
2721 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2725 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2726 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2752 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
[all …]
DLegalizeDAG.cpp905 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
906 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
973 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
985 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
995 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
1000 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
1058 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
1091 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
1126 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
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DLegalizeIntegerTypes.cpp473 ISD::LoadExtType ExtType = in PromoteIntRes_LOAD() local
476 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
2004 ISD::LoadExtType ExtType = N->getExtensionType(); in ExpandIntRes_LOAD() local
2017 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
2024 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
2031 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
2035 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
2053 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
2071 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
2100 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, in ExpandIntRes_LOAD()
DSelectionDAG.cpp230 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType() argument
231 switch (ExtType) { in getExtForLoadExtType()
2727 unsigned ExtType = LD->getExtensionType(); in ComputeNumSignBits() local
2728 switch (ExtType) { in ComputeNumSignBits()
5039 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
5068 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); in getLoad()
5072 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
5077 ExtType = ISD::NON_EXTLOAD; in getLoad()
5078 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
5103 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), in getLoad()
[all …]
DDAGCombiner.cpp216 ISD::NodeType ExtType);
967 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteOperand() local
972 return DAG.getExtLoad(ExtType, dl, PVT, in PromoteOperand()
1189 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteLoad() local
1193 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, in PromoteLoad()
5844 ISD::NodeType ExtType) { in ExtendSetCCUses() argument
5855 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); in ExtendSetCCUses()
5904 ISD::LoadExtType ExtType = in CombineExtLoad() local
5910 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) && in CombineExtLoad()
5916 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT)) in CombineExtLoad()
[all …]
DLegalizeTypes.h771 LoadSDNode *LD, ISD::LoadExtType ExtType);
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h838 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
843 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
848 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
855 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h133 ISD::LoadExtType ExtType,
DAMDGPUISelLowering.cpp1406 ISD::LoadExtType ExtType = Load->getExtensionType(); in LowerLOAD() local
1410 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) { in LowerLOAD()
1432 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32)) in LowerLOAD()
1463 if (ExtType == ISD::SEXTLOAD) { in LowerLOAD()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2495 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in LowerFormalArguments() local
2505 ExtType = ISD::SEXTLOAD; in LowerFormalArguments()
2508 ExtType = ISD::ZEXTLOAD; in LowerFormalArguments()
2511 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
2516 ExtType, DL, VA.getLocVT(), Chain, FIN, in LowerFormalArguments()
8235 unsigned ExtType = LHS.getOpcode(); in performAddSubLongCombine() local
8244 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); in performAddSubLongCombine()
8250 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); in performAddSubLongCombine()
9184 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { in checkValueWidth() argument
9185 ExtType = ISD::NON_EXTLOAD; in checkValueWidth()
[all …]
DAArch64FastISel.cpp55 AArch64_AM::ShiftExtendType ExtType; member in __anoncec764240111::AArch64FastISel::Address
66 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend), in Address()
70 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; } in setExtendType()
71 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; } in getExtendType()
175 AArch64_AM::ShiftExtendType ExtType,
1366 AArch64_AM::ShiftExtendType ExtType, in emitAddSub_rx() argument
1402 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
DAArch64ISelDAGToDAG.cpp1053 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
1058 if (ExtType == ISD::NON_EXTLOAD) in SelectIndexedLoad()
1060 else if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
1070 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
1083 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
DAArch64InstrInfo.cpp1285 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); in isScaledAddr() local
1286 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); in isScaledAddr()
/external/llvm/lib/Target/X86/
DX86InstrInfo.td938 ISD::LoadExtType ExtType = LD->getExtensionType();
939 if (ExtType == ISD::NON_EXTLOAD)
941 if (ExtType == ISD::EXTLOAD)
948 ISD::LoadExtType ExtType = LD->getExtensionType();
949 if (ExtType == ISD::EXTLOAD)
956 ISD::LoadExtType ExtType = LD->getExtensionType();
957 if (ExtType == ISD::NON_EXTLOAD)
959 if (ExtType == ISD::EXTLOAD)
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2196 ISD::LoadExtType ExtType = LD->getExtensionType(); in lowerLOAD() local
2206 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { in lowerLOAD()
2225 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || in lowerLOAD()
2226 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
2229 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp4712 Instruction::CastOps ExtType = Instruction::ZExt; in optimizeSwitchInst() local
4715 ExtType = Instruction::SExt; in optimizeSwitchInst()
4717 auto *ExtInst = CastInst::Create(ExtType, Cond, NewType); in optimizeSwitchInst()
4722 APInt WideConst = (ExtType == Instruction::ZExt) ? in optimizeSwitchInst()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp4003 unsigned ExtType = in PerformANDCombine() local
4006 if (ExtType == ISD::SEXTLOAD) { in PerformANDCombine()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp1612 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ? in adjustSubwordCmp() local
1616 Load->getExtensionType() != ExtType) in adjustSubwordCmp()
1617 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, in adjustSubwordCmp()