| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV5.td | 77 [(set F32:$dst,
90 [(set F32:$dst, fpimm:$src1)]>,
104 [(set F32:$dst, fpimm:$src1)]>,
145 defm: Storex_pat<store, F32, s30_2ImmPred, S2_storeri_io>;
147 def: Storex_simple_pat<store, F32, S2_storeri_io>;
179 def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
180 (F2_sfadd F32:$src1, F32:$src2)>;
182 def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
183 (F2_sfsub F32:$src1, F32:$src2)>;
185 def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
[all …]
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| D | HexagonIntrinsics.td | 130 : Pat<(IntID F32:$Rs),
131 (MI F32:$Rs)>;
135 : Pat<(IntID F32:$Rs, ImmPred:$It),
136 (MI F32:$Rs, ImmPred:$It)>;
139 : Pat<(IntID F32:$Rs, F32:$Rt),
140 (MI F32:$Rs, F32:$Rt)>;
147 : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
148 (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
151 : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
152 (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrConv.td | 40 def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
41 [(set I32:$dst, (fp_to_sint F32:$src))],
43 def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
44 [(set I32:$dst, (fp_to_uint F32:$src))],
46 def I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src),
47 [(set I64:$dst, (fp_to_sint F32:$src))],
49 def I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src),
50 [(set I64:$dst, (fp_to_uint F32:$src))],
66 def F32_CONVERT_S_I32 : I<(outs F32:$dst), (ins I32:$src),
67 [(set F32:$dst, (sint_to_fp I32:$src))],
[all …]
|
| D | WebAssemblyInstrFloat.td | 42 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
43 (COPYSIGN_F64 F64:$lhs, (F64_PROMOTE_F32 F32:$rhs))>;
44 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
45 (COPYSIGN_F32 F32:$lhs, (F32_DEMOTE_F64 F64:$rhs))>;
80 def SELECT_F32 : I<(outs F32:$dst), (ins I32:$cond, F32:$lhs, F32:$rhs),
81 [(set F32:$dst, (select I32:$cond, F32:$lhs, F32:$rhs))],
92 def : Pat<(select (i32 (setne I32:$cond, 0)), F32:$lhs, F32:$rhs),
93 (SELECT_F32 I32:$cond, F32:$lhs, F32:$rhs)>;
98 def : Pat<(select (i32 (seteq I32:$cond, 0)), F32:$lhs, F32:$rhs),
99 (SELECT_F32 I32:$cond, F32:$rhs, F32:$lhs)>;
|
| D | WebAssemblyInstrFormats.td | 49 def _F32 : I<(outs F32:$dst), (ins F32:$src),
50 [(set F32:$dst, (node F32:$src))],
57 def _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs),
58 [(set F32:$dst, (node F32:$lhs, F32:$rhs))],
73 def _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs),
74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
|
| D | WebAssemblyInstrInfo.td | 88 defm : ARGUMENT<F32>;
113 defm : LOCAL<F32>;
123 def CONST_F32 : I<(outs F32:$res), (ins f32imm:$imm),
124 [(set F32:$res, fpimm:$imm)],
|
| D | WebAssemblyInstrMemory.td | 38 def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr), [],
332 def STORE_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr, F32:$val), [],
342 def : Pat<(store F32:$val, I32:$addr), (STORE_F32 0, I32:$addr, F32:$val)>;
350 def : Pat<(store F32:$val, (regPlusImm imm:$off, I32:$addr)),
351 (STORE_F32 imm:$off, I32:$addr, F32:$val)>;
358 def : Pat<(store F32:$val, (regPlusImm tglobaladdr:$off, I32:$addr)),
359 (STORE_F32 tglobaladdr:$off, I32:$addr, F32:$val)>;
366 def : Pat<(store F32:$val, (regPlusImm texternalsym:$off, I32:$addr)),
367 (STORE_F32 texternalsym:$off, I32:$addr, F32:$val)>;
376 def : Pat<(store F32:$val, imm:$off),
[all …]
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| D | WebAssemblyRegisterInfo.td | 57 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
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| D | WebAssemblyInstrCall.td | 39 defm : CALL<F32, "f32.">;
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| D | WebAssemblyInstrControl.td | 71 defm : RETURN<F32>;
|
| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/engines/ |
| D | TwofishEngine.java | 377 A = F32(q, k32e); in setKey()
378 B = F32(q+SK_BUMP, k32o); in setKey()
523 private int F32(int x, int[] k32) in F32() method in TwofishEngine
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 209 def D16 : SparcReg< 1, "F32">;
235 def Q8 : Rq< 1, "F32", [D16, D17]>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 443 // ASIMD FP divide, D-form, F32
445 // ASIMD FP divide, Q-form, F32
451 // ASIMD FP square root, D-form, F32
453 // ASIMD FP square root, Q-form, F32
|
| /external/valgrind/docs/internals/ |
| D | register-uses.txt | 132 holding the address for F32/F64 spills, since the VFP load/store
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 2791 enum VFPType { S32, U32, F32, F64 }; enumerator
2812 case F32: in IsIntegerVFPType()
2824 case F32: in IsDoubleVFPType()
2914 emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond)); in vcvt_f32_s32()
2946 emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond)); in vcvt_f64_f32()
2954 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); in vcvt_f32_f64()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 725 // F32 Approximate reciprocal
740 // F32 Approximate division
767 // F32 Semi-accurate reciprocal
784 // F32 Semi-accurate division
811 // F32 Accurate reciprocal
826 // F32 Accurate division
854 // F32 rsqrt
|
| /external/valgrind/VEX/priv/ |
| D | ir_defs.c | 81 case Ico_F32: u.f32 = con->Ico.F32; in ppIRConst()
1716 c->Ico.F32 = f32; in IRConst_F32()
2254 case Ico_F32: return IRConst_F32(c->Ico.F32); in deepCopyIRConst()
4614 case Ico_F32: return toBool( c1->Ico.F32 == c2->Ico.F32 ); in eqIRConst()
|
| /external/valgrind/VEX/pub/ |
| D | libvex_ir.h | 300 Float F32; member
|
| /external/icu/icu4c/source/data/unidata/norm2/ |
| D | nfc.txt | 1042 1F32=1F30 0300
|
| D | nfkc_cf.txt | 891 1F3A>1F32
1505 2F32>5E72
|
| /external/icu/icu4c/source/data/sprep/ |
| D | rfc3722.txt | 1055 1F3A; 1F32; MAP
|
| D | rfc3920node.txt | 1055 1F3A; 1F32; MAP
|
| D | rfc4518ci.txt | 1022 1F3A; 1F32; MAP
|
| /external/icu/icu4c/source/test/testdata/ |
| D | nfs4_cs_prep_ci.txt | 1045 1F3A; 1F32; MAP
|
| D | nfs4_cis_prep.txt | 1045 1F3A; 1F32; MAP
|