Searched refs:FGETSIGN (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 258 FGETSIGN, enumerator
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| /external/llvm/test/CodeGen/X86/ |
| D | movmsk.ll | 84 ; FIXME: This should also use movmskps; we don't form the FGETSIGN node
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 204 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
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| D | TargetLowering.cpp | 1073 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); in SimplifyDemandedBits()
1074 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
1081 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); in SimplifyDemandedBits()
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| D | SelectionDAG.cpp | 2355 case ISD::FGETSIGN: in computeKnownBits()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 786 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 428 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 666 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
719 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 543 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
544 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
20094 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 657 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
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