| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 523 FMINNUM, FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 645 ISD = ISD::FMINNUM; in getIntrinsicInstrCost()
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| D | SelectionDAG.h | 1100 case ISD::FMINNUM:
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
256 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
1906 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
1995 case ISD::FMINNUM: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 92 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
342 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering()
963 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 153 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
999 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
1874 case ISD::FMINNUM: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 302 case ISD::FMINNUM: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2481 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
2483 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) in visitSelect()
2484 Opc = ISD::FMINNUM; in visitSelect()
2488 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? in visitSelect()
2489 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
4784 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, in visitIntrinsicCall()
5801 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| D | LegalizeVectorTypes.cpp | 110 case ISD::FMINNUM: in ScalarizeVectorResult()
670 case ISD::FMINNUM: in SplitVectorResult()
2034 case ISD::FMINNUM: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 4021 case ISD::FMINNUM: in ConvertNodeToLibcall()
4401 case ISD::FMINNUM: in PromoteNode()
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| D | DAGCombiner.cpp | 1427 case ISD::FMINNUM: return visitFMINNUM(N); in visit()
4994 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; in combineMinNumMaxNum()
5005 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; in combineMinNumMaxNum()
9247 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0); in visitFMINNUM()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 788 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
846 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 305 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
397 setOperationAction(ISD::FMINNUM, Ty, Legal); in AArch64TargetLowering()
703 ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
8411 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
8801 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in tryMatchAcrossLaneShuffleForReduction()
8882 case ISD::FMINNUM: in tryMatchAcrossLaneShuffleForReduction()
8947 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine()
8958 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in performAcrossLaneMinMaxReductionCombine()
8985 (Op == ISD::FMINNUM && CC != ISD::SETOLT && CC != ISD::SETOLE && in performAcrossLaneMinMaxReductionCombine()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 424 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 979 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in ARMTargetLowering()
981 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal); in ARMTargetLowering()
983 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in ARMTargetLowering()
993 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in ARMTargetLowering()
2833 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1762 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 705 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering()
751 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 678 setOperationAction(ISD::FMINNUM, MVT::f80, Expand); in X86TargetLowering()
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