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Searched refs:FPU (Results 1 – 25 of 75) sorted by relevance

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/external/elfutils/tests/
Drun-addrcfi.sh68 FPU-control reg37 (%fctrl): undefined
69 FPU-control reg38 (%fstat): undefined
70 FPU-control reg39 (%mxcsr): undefined
115 FPU-control reg37 (%fctrl): undefined
116 FPU-control reg38 (%fstat): undefined
117 FPU-control reg39 (%mxcsr): undefined
334 FPU reg32 (f0): undefined
335 FPU reg33 (f1): undefined
336 FPU reg34 (f2): undefined
337 FPU reg35 (f3): undefined
[all …]
/external/llvm/test/MC/Mips/
Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dmodule-hardfloat.s12 # CHECK-OBJ: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
Dmips_abi_flags_xx_set.s34 # CHECK-OBJ-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
Dmips_abi_flags_xx.s42 # CHECK-OBJ-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
/external/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll55 …e=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-FP16
56 …inux-gnueabi -mattr=-neon,+vfp3,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-D16-FP16
57 …linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD
58 …bi -mattr=-neon,+vfp3,+fp-only-sp,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD-FP16
59 …-mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16
177 ;; The default choice made by llc is for a V6 CPU without an FPU.
180 ;; FPU support!
196 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
211 ;; The default choice made by llc is for a V6M CPU without an FPU.
214 ;; FPU support!
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMELFStreamer.cpp86 void emitFPU(unsigned FPU) override;
206 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) { in emitFPU() argument
207 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
277 unsigned FPU; member in __anond09109f60111::ARMTargetELFStreamer
381 void emitFPU(unsigned FPU) override;
393 : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::FK_INVALID), in ARMTargetELFStreamer()
778 FPU = Value; in emitFPU()
781 switch (FPU) { in emitFPUDefaultAttributes()
907 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
944 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
[all …]
DARMTargetStreamer.cpp68 void ARMTargetStreamer::emitFPU(unsigned FPU) {} in emitFPU() argument
/external/llvm/lib/Support/
DTargetParser.cpp382 static StringRef getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
383 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
396 .Default(FPU); in getFPUSynonym()
479 unsigned llvm::ARM::parseFPU(StringRef FPU) { in parseFPU() argument
480 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td50 // Mips 32-bit FPU Registers
53 // Mips 64-bit (aliased) FPU Registers
155 /// Mips Single point precision FPU Registers
163 /// Mips Double point precision FPU Registers (aliased
170 /// Mips Double point precision FPU Registers in MFP64 mode.
176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
393 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
/external/llvm/test/MC/ARM/
Ddirective-fpu-diagnostics.s8 @ CHECK: error: Unknown FPU name
Ddirective-fpu-softvfp.s3 @ Check softvfp as the FPU name.
/external/llvm/lib/Target/PowerPC/
DPPCScheduleP8.td28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
42 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
45 // FPU, so keep in mind that FPU==VSU.
387 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
DPPCScheduleE500mc.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
37 def E500_FPU_0 : FuncUnit; // FPU pipeline
DPPCScheduleE5500.td27 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
40 def E5500_FPU_0 : FuncUnit; // FPU pipeline
/external/llvm/include/llvm/Support/
DTargetParser.h133 unsigned parseFPU(StringRef FPU);
/external/llvm/lib/Target/X86/
DX86ScheduleBtVer2.td21 let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
/external/llvm/test/CodeGen/X86/
Dvec_fneg.ll25 ; If we're bitcasting an integer to an FP vector, we should avoid the FPU/vector unit entirely.
/external/clang/lib/Basic/
DTargets.cpp4216 unsigned FPU : 5; member in __anond4862fe70111::ARMTargetInfo
4570 FPU = 0; in handleTargetFeatures()
4587 FPU |= VFP2FPU; in handleTargetFeatures()
4590 FPU |= VFP3FPU; in handleTargetFeatures()
4593 FPU |= VFP4FPU; in handleTargetFeatures()
4596 FPU |= FPARMV8; in handleTargetFeatures()
4599 FPU |= NeonFPU; in handleTargetFeatures()
4642 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { in handleTargetFeatures()
4667 .Case("neon", (FPU & NeonFPU) && !SoftFloat) in hasFeature()
4819 if (FPUModeIsVFP((FPUMode) FPU)) { in getTargetDefines()
[all …]
/external/clang/docs/
DCrossCompilation.rst100 Finally, the ABI option is something that will pick default CPU/FPU,
104 CPU, FPU, ABI
108 be compiling to. For every architecture, a default set of CPU/FPU/ABI
/external/llvm/test/CodeGen/SPARC/
Dspill.ll37 ;; For float/double tests, a call is a suitable clobber as *all* FPU
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg.ll58 ; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode).
/external/v8/test/webkit/
Dwebkit.status67 # Too slow for mips big-endian boards on bots (no FPU).

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