1 /*
2  * SyncLink Multiprotocol Serial Adapter Driver
3  *
4  * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $
5  *
6  * Copyright (C) 1998-2000 by Microgate Corporation
7  *
8  * Redistribution of this file is permitted under
9  * the terms of the GNU Public License (GPL)
10  */
11 
12 #ifndef _UAPI_SYNCLINK_H_
13 #define _UAPI_SYNCLINK_H_
14 #define SYNCLINK_H_VERSION 3.6
15 
16 #include <linux/types.h>
17 
18 #define BIT0	0x0001
19 #define BIT1	0x0002
20 #define BIT2	0x0004
21 #define BIT3	0x0008
22 #define BIT4	0x0010
23 #define BIT5	0x0020
24 #define BIT6	0x0040
25 #define BIT7	0x0080
26 #define BIT8	0x0100
27 #define BIT9	0x0200
28 #define BIT10	0x0400
29 #define BIT11	0x0800
30 #define BIT12	0x1000
31 #define BIT13	0x2000
32 #define BIT14	0x4000
33 #define BIT15	0x8000
34 #define BIT16	0x00010000
35 #define BIT17	0x00020000
36 #define BIT18	0x00040000
37 #define BIT19	0x00080000
38 #define BIT20	0x00100000
39 #define BIT21	0x00200000
40 #define BIT22	0x00400000
41 #define BIT23	0x00800000
42 #define BIT24	0x01000000
43 #define BIT25	0x02000000
44 #define BIT26	0x04000000
45 #define BIT27	0x08000000
46 #define BIT28	0x10000000
47 #define BIT29	0x20000000
48 #define BIT30	0x40000000
49 #define BIT31	0x80000000
50 
51 
52 #define HDLC_MAX_FRAME_SIZE	65535
53 #define MAX_ASYNC_TRANSMIT	4096
54 #define MAX_ASYNC_BUFFER_SIZE	4096
55 
56 #define ASYNC_PARITY_NONE		0
57 #define ASYNC_PARITY_EVEN		1
58 #define ASYNC_PARITY_ODD		2
59 #define ASYNC_PARITY_SPACE		3
60 
61 #define HDLC_FLAG_UNDERRUN_ABORT7	0x0000
62 #define HDLC_FLAG_UNDERRUN_ABORT15	0x0001
63 #define HDLC_FLAG_UNDERRUN_FLAG		0x0002
64 #define HDLC_FLAG_UNDERRUN_CRC		0x0004
65 #define HDLC_FLAG_SHARE_ZERO		0x0010
66 #define HDLC_FLAG_AUTO_CTS		0x0020
67 #define HDLC_FLAG_AUTO_DCD		0x0040
68 #define HDLC_FLAG_AUTO_RTS		0x0080
69 #define HDLC_FLAG_RXC_DPLL		0x0100
70 #define HDLC_FLAG_RXC_BRG		0x0200
71 #define HDLC_FLAG_RXC_TXCPIN		0x8000
72 #define HDLC_FLAG_RXC_RXCPIN		0x0000
73 #define HDLC_FLAG_TXC_DPLL		0x0400
74 #define HDLC_FLAG_TXC_BRG		0x0800
75 #define HDLC_FLAG_TXC_TXCPIN		0x0000
76 #define HDLC_FLAG_TXC_RXCPIN		0x0008
77 #define HDLC_FLAG_DPLL_DIV8		0x1000
78 #define HDLC_FLAG_DPLL_DIV16		0x2000
79 #define HDLC_FLAG_DPLL_DIV32		0x0000
80 #define HDLC_FLAG_HDLC_LOOPMODE		0x4000
81 
82 #define HDLC_CRC_NONE			0
83 #define HDLC_CRC_16_CCITT		1
84 #define HDLC_CRC_32_CCITT		2
85 #define HDLC_CRC_MASK			0x00ff
86 #define HDLC_CRC_RETURN_EX		0x8000
87 
88 #define RX_OK				0
89 #define RX_CRC_ERROR			1
90 
91 #define HDLC_TXIDLE_FLAGS		0
92 #define HDLC_TXIDLE_ALT_ZEROS_ONES	1
93 #define HDLC_TXIDLE_ZEROS		2
94 #define HDLC_TXIDLE_ONES		3
95 #define HDLC_TXIDLE_ALT_MARK_SPACE	4
96 #define HDLC_TXIDLE_SPACE		5
97 #define HDLC_TXIDLE_MARK		6
98 #define HDLC_TXIDLE_CUSTOM_8            0x10000000
99 #define HDLC_TXIDLE_CUSTOM_16           0x20000000
100 
101 #define HDLC_ENCODING_NRZ			0
102 #define HDLC_ENCODING_NRZB			1
103 #define HDLC_ENCODING_NRZI_MARK			2
104 #define HDLC_ENCODING_NRZI_SPACE		3
105 #define HDLC_ENCODING_NRZI			HDLC_ENCODING_NRZI_SPACE
106 #define HDLC_ENCODING_BIPHASE_MARK		4
107 #define HDLC_ENCODING_BIPHASE_SPACE		5
108 #define HDLC_ENCODING_BIPHASE_LEVEL		6
109 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL	7
110 
111 #define HDLC_PREAMBLE_LENGTH_8BITS	0
112 #define HDLC_PREAMBLE_LENGTH_16BITS	1
113 #define HDLC_PREAMBLE_LENGTH_32BITS	2
114 #define HDLC_PREAMBLE_LENGTH_64BITS	3
115 
116 #define HDLC_PREAMBLE_PATTERN_NONE	0
117 #define HDLC_PREAMBLE_PATTERN_ZEROS	1
118 #define HDLC_PREAMBLE_PATTERN_FLAGS	2
119 #define HDLC_PREAMBLE_PATTERN_10	3
120 #define HDLC_PREAMBLE_PATTERN_01	4
121 #define HDLC_PREAMBLE_PATTERN_ONES	5
122 
123 #define MGSL_MODE_ASYNC		1
124 #define MGSL_MODE_HDLC		2
125 #define MGSL_MODE_MONOSYNC	3
126 #define MGSL_MODE_BISYNC	4
127 #define MGSL_MODE_RAW		6
128 #define MGSL_MODE_BASE_CLOCK    7
129 #define MGSL_MODE_XSYNC         8
130 
131 #define MGSL_BUS_TYPE_ISA	1
132 #define MGSL_BUS_TYPE_EISA	2
133 #define MGSL_BUS_TYPE_PCI	5
134 
135 #define MGSL_INTERFACE_MASK     0xf
136 #define MGSL_INTERFACE_DISABLE  0
137 #define MGSL_INTERFACE_RS232    1
138 #define MGSL_INTERFACE_V35      2
139 #define MGSL_INTERFACE_RS422    3
140 #define MGSL_INTERFACE_RTS_EN   0x10
141 #define MGSL_INTERFACE_LL       0x20
142 #define MGSL_INTERFACE_RL       0x40
143 #define MGSL_INTERFACE_MSB_FIRST 0x80
144 
145 typedef struct _MGSL_PARAMS
146 {
147 	/* Common */
148 
149 	unsigned long	mode;		/* Asynchronous or HDLC */
150 	unsigned char	loopback;	/* internal loopback mode */
151 
152 	/* HDLC Only */
153 
154 	unsigned short	flags;
155 	unsigned char	encoding;	/* NRZ, NRZI, etc. */
156 	unsigned long	clock_speed;	/* external clock speed in bits per second */
157 	unsigned char	addr_filter;	/* receive HDLC address filter, 0xFF = disable */
158 	unsigned short	crc_type;	/* None, CRC16-CCITT, or CRC32-CCITT */
159 	unsigned char	preamble_length;
160 	unsigned char	preamble;
161 
162 	/* Async Only */
163 
164 	unsigned long	data_rate;	/* bits per second */
165 	unsigned char	data_bits;	/* 7 or 8 data bits */
166 	unsigned char	stop_bits;	/* 1 or 2 stop bits */
167 	unsigned char	parity;		/* none, even, or odd */
168 
169 } MGSL_PARAMS, *PMGSL_PARAMS;
170 
171 #define MICROGATE_VENDOR_ID 0x13c0
172 #define SYNCLINK_DEVICE_ID 0x0010
173 #define MGSCC_DEVICE_ID 0x0020
174 #define SYNCLINK_SCA_DEVICE_ID 0x0030
175 #define SYNCLINK_GT_DEVICE_ID 0x0070
176 #define SYNCLINK_GT4_DEVICE_ID 0x0080
177 #define SYNCLINK_AC_DEVICE_ID  0x0090
178 #define SYNCLINK_GT2_DEVICE_ID 0x00A0
179 #define MGSL_MAX_SERIAL_NUMBER 30
180 
181 /*
182 ** device diagnostics status
183 */
184 
185 #define DiagStatus_OK				0
186 #define DiagStatus_AddressFailure		1
187 #define DiagStatus_AddressConflict		2
188 #define DiagStatus_IrqFailure			3
189 #define DiagStatus_IrqConflict			4
190 #define DiagStatus_DmaFailure			5
191 #define DiagStatus_DmaConflict			6
192 #define DiagStatus_PciAdapterNotFound		7
193 #define DiagStatus_CantAssignPciResources	8
194 #define DiagStatus_CantAssignPciMemAddr		9
195 #define DiagStatus_CantAssignPciIoAddr		10
196 #define DiagStatus_CantAssignPciIrq		11
197 #define DiagStatus_MemoryError			12
198 
199 #define SerialSignal_DCD            0x01     /* Data Carrier Detect */
200 #define SerialSignal_TXD            0x02     /* Transmit Data */
201 #define SerialSignal_RI             0x04     /* Ring Indicator */
202 #define SerialSignal_RXD            0x08     /* Receive Data */
203 #define SerialSignal_CTS            0x10     /* Clear to Send */
204 #define SerialSignal_RTS            0x20     /* Request to Send */
205 #define SerialSignal_DSR            0x40     /* Data Set Ready */
206 #define SerialSignal_DTR            0x80     /* Data Terminal Ready */
207 
208 
209 /*
210  * Counters of the input lines (CTS, DSR, RI, CD) interrupts
211  */
212 struct mgsl_icount {
213 	__u32	cts, dsr, rng, dcd, tx, rx;
214 	__u32	frame, parity, overrun, brk;
215 	__u32	buf_overrun;
216 	__u32	txok;
217 	__u32	txunder;
218 	__u32	txabort;
219 	__u32	txtimeout;
220 	__u32	rxshort;
221 	__u32	rxlong;
222 	__u32	rxabort;
223 	__u32	rxover;
224 	__u32	rxcrc;
225 	__u32	rxok;
226 	__u32	exithunt;
227 	__u32	rxidle;
228 };
229 
230 struct gpio_desc {
231 	__u32 state;
232 	__u32 smask;
233 	__u32 dir;
234 	__u32 dmask;
235 };
236 
237 #define DEBUG_LEVEL_DATA	1
238 #define DEBUG_LEVEL_ERROR 	2
239 #define DEBUG_LEVEL_INFO  	3
240 #define DEBUG_LEVEL_BH    	4
241 #define DEBUG_LEVEL_ISR		5
242 
243 /*
244 ** Event bit flags for use with MgslWaitEvent
245 */
246 
247 #define MgslEvent_DsrActive	0x0001
248 #define MgslEvent_DsrInactive	0x0002
249 #define MgslEvent_Dsr		0x0003
250 #define MgslEvent_CtsActive	0x0004
251 #define MgslEvent_CtsInactive	0x0008
252 #define MgslEvent_Cts		0x000c
253 #define MgslEvent_DcdActive	0x0010
254 #define MgslEvent_DcdInactive	0x0020
255 #define MgslEvent_Dcd		0x0030
256 #define MgslEvent_RiActive	0x0040
257 #define MgslEvent_RiInactive	0x0080
258 #define MgslEvent_Ri		0x00c0
259 #define MgslEvent_ExitHuntMode	0x0100
260 #define MgslEvent_IdleReceived	0x0200
261 
262 /* Private IOCTL codes:
263  *
264  * MGSL_IOCSPARAMS	set MGSL_PARAMS structure values
265  * MGSL_IOCGPARAMS	get current MGSL_PARAMS structure values
266  * MGSL_IOCSTXIDLE	set current transmit idle mode
267  * MGSL_IOCGTXIDLE	get current transmit idle mode
268  * MGSL_IOCTXENABLE	enable or disable transmitter
269  * MGSL_IOCRXENABLE	enable or disable receiver
270  * MGSL_IOCTXABORT	abort transmitting frame (HDLC)
271  * MGSL_IOCGSTATS	return current statistics
272  * MGSL_IOCWAITEVENT	wait for specified event to occur
273  * MGSL_LOOPTXDONE	transmit in HDLC LoopMode done
274  * MGSL_IOCSIF          set the serial interface type
275  * MGSL_IOCGIF          get the serial interface type
276  */
277 #define MGSL_MAGIC_IOC	'm'
278 #define MGSL_IOCSPARAMS		_IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS)
279 #define MGSL_IOCGPARAMS		_IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS)
280 #define MGSL_IOCSTXIDLE		_IO(MGSL_MAGIC_IOC,2)
281 #define MGSL_IOCGTXIDLE		_IO(MGSL_MAGIC_IOC,3)
282 #define MGSL_IOCTXENABLE	_IO(MGSL_MAGIC_IOC,4)
283 #define MGSL_IOCRXENABLE	_IO(MGSL_MAGIC_IOC,5)
284 #define MGSL_IOCTXABORT		_IO(MGSL_MAGIC_IOC,6)
285 #define MGSL_IOCGSTATS		_IO(MGSL_MAGIC_IOC,7)
286 #define MGSL_IOCWAITEVENT	_IOWR(MGSL_MAGIC_IOC,8,int)
287 #define MGSL_IOCCLRMODCOUNT	_IO(MGSL_MAGIC_IOC,15)
288 #define MGSL_IOCLOOPTXDONE	_IO(MGSL_MAGIC_IOC,9)
289 #define MGSL_IOCSIF		_IO(MGSL_MAGIC_IOC,10)
290 #define MGSL_IOCGIF		_IO(MGSL_MAGIC_IOC,11)
291 #define MGSL_IOCSGPIO		_IOW(MGSL_MAGIC_IOC,16,struct gpio_desc)
292 #define MGSL_IOCGGPIO		_IOR(MGSL_MAGIC_IOC,17,struct gpio_desc)
293 #define MGSL_IOCWAITGPIO	_IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc)
294 #define MGSL_IOCSXSYNC		_IO(MGSL_MAGIC_IOC, 19)
295 #define MGSL_IOCGXSYNC		_IO(MGSL_MAGIC_IOC, 20)
296 #define MGSL_IOCSXCTRL		_IO(MGSL_MAGIC_IOC, 21)
297 #define MGSL_IOCGXCTRL		_IO(MGSL_MAGIC_IOC, 22)
298 
299 
300 #endif /* _UAPI_SYNCLINK_H_ */
301