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Searched refs:I32 (Results 1 – 25 of 32) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrMemory.td34 def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr), [],
36 def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr), [],
38 def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr), [],
40 def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr), [],
46 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr)>;
47 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr)>;
48 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr)>;
49 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr)>;
52 def : Pat<(i32 (load (regPlusImm imm:$off, I32:$addr))),
54 def : Pat<(i64 (load (regPlusImm imm:$off, I32:$addr))),
[all …]
DWebAssemblyInstrInteger.td60 def : Pat<(ctlz_zero_undef I32:$src), (CLZ_I32 I32:$src)>;
62 def : Pat<(cttz_zero_undef I32:$src), (CTZ_I32 I32:$src)>;
67 def SELECT_I32 : I<(outs I32:$dst), (ins I32:$cond, I32:$lhs, I32:$rhs),
68 [(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))],
70 def SELECT_I64 : I<(outs I64:$dst), (ins I32:$cond, I64:$lhs, I64:$rhs),
71 [(set I64:$dst, (select I32:$cond, I64:$lhs, I64:$rhs))],
79 def : Pat<(select (i32 (setne I32:$cond, 0)), I32:$lhs, I32:$rhs),
80 (SELECT_I32 I32:$cond, I32:$lhs, I32:$rhs)>;
81 def : Pat<(select (i32 (setne I32:$cond, 0)), I64:$lhs, I64:$rhs),
82 (SELECT_I64 I32:$cond, I64:$lhs, I64:$rhs)>;
[all …]
DWebAssemblyInstrFormats.td33 def _I32 : I<(outs I32:$dst), (ins I32:$src),
34 [(set I32:$dst, (node I32:$src))],
41 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
42 [(set I32:$dst, (node I32:$lhs, I32:$rhs))],
65 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
66 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
68 def _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs),
69 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
73 def _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs),
74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
[all …]
DWebAssemblyInstrConv.td18 def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src),
19 [(set I32:$dst, (trunc I64:$src))],
22 def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src),
23 [(set I64:$dst, (sext I32:$src))],
25 def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src),
26 [(set I64:$dst, (zext I32:$src))],
34 def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>;
40 def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
41 [(set I32:$dst, (fp_to_sint F32:$src))],
43 def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
[all …]
DWebAssemblyInstrControl.td19 def BR_IF : I<(outs), (ins I32:$cond, bb_op:$dst),
20 [(brcond I32:$cond, bb:$dst)],
23 def BR_UNLESS : I<(outs), (ins I32:$cond, bb_op:$dst), [],
34 def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
35 (BR_IF I32:$cond, bb_op:$dst)>;
36 def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
37 (BR_UNLESS I32:$cond, bb_op:$dst)>;
45 def TABLESWITCH_I32 : I<(outs), (ins I32:$index, bb_op:$default, variable_ops),
46 [(WebAssemblytableswitch I32:$index, bb:$default)],
69 defm : RETURN<I32>;
DWebAssemblyInstrFloat.td80 def SELECT_F32 : I<(outs F32:$dst), (ins I32:$cond, F32:$lhs, F32:$rhs),
81 [(set F32:$dst, (select I32:$cond, F32:$lhs, F32:$rhs))],
83 def SELECT_F64 : I<(outs F64:$dst), (ins I32:$cond, F64:$lhs, F64:$rhs),
84 [(set F64:$dst, (select I32:$cond, F64:$lhs, F64:$rhs))],
92 def : Pat<(select (i32 (setne I32:$cond, 0)), F32:$lhs, F32:$rhs),
93 (SELECT_F32 I32:$cond, F32:$lhs, F32:$rhs)>;
94 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
95 (SELECT_F64 I32:$cond, F64:$lhs, F64:$rhs)>;
98 def : Pat<(select (i32 (seteq I32:$cond, 0)), F32:$lhs, F32:$rhs),
99 (SELECT_F32 I32:$cond, F32:$rhs, F32:$lhs)>;
[all …]
DWebAssemblyInstrCall.td32 def CALL_INDIRECT_#vt : I<(outs vt:$dst), (ins I32:$callee, variable_ops),
33 [(set vt:$dst, (WebAssemblycall1 I32:$callee))],
37 defm : CALL<I32, "i32.">;
45 def CALL_INDIRECT_VOID : I<(outs), (ins I32:$callee, variable_ops),
46 [(WebAssemblycall0 I32:$callee)],
DWebAssemblyInstrInfo.td86 defm : ARGUMENT<I32>;
111 defm : LOCAL<I32>;
117 def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm),
118 [(set I32:$res, imm:$imm)],
DWebAssemblyRegisterInfo.td55 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
34 (MI I32:$Rs, ImmPred:$It)>;
37 : Pat<(IntID ImmPred:$Is, I32:$Rt),
38 (MI ImmPred:$Is, I32:$Rt)>;
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
49 : Pat <(IntID I32:$Rs, I32:$Rt),
50 (MI I32:$Rs, I32:$Rt)>;
[all …]
DHexagonInstrInfoVector.td138 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
142 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
226 : Pat <(Op Value:$Rs, I32:$Rt),
227 (MI Value:$Rs, I32:$Rt)>;
395 def: Pat<(i64 (HexagonVSXTBH I32:$Rs)), (S2_vsxtbh I32:$Rs)>;
396 def: Pat<(i64 (HexagonVSXTBW I32:$Rs)), (S2_vsxthw I32:$Rs)>;
501 def: Pat<(truncstorev2i16 V2I32:$Rs, I32:$Rt),
502 (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
505 def: Pat<(truncstorev4i8 V4I16:$Rs, I32:$Rt),
506 (S2_storeri_io I32:$Rt, 0, (S2_vtrunehb V4I16:$Rs))>;
[all …]
DHexagonInstrInfo.td23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
418 def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
419 (i32 (A2_addi I32:$Rs, imm:$s16))>;
693 def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
694 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
696 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
697 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
[all …]
DHexagonInstrInfoV5.td129 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
619 uint_to_fp, F32, I32>;
621 sint_to_fp, F32, I32>;
627 uint_to_fp, F64, I32>;
629 sint_to_fp, F64, I32>;
633 fp_to_uint, I32, F64, ":chop">;
635 fp_to_sint, I32, F64, ":chop">;
637 fp_to_uint, I32, F32, ":chop">;
639 fp_to_sint, I32, F32, ":chop">;
660 fp_to_uint, I32, F64>;
[all …]
DHexagonInstrInfoV4.td1044 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1045 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1046 def: Storexs_pat<store, I32, S4_storeri_rr>;
1851 def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)),
1852 (L2_loadri_io I32:$got, imm:$addr)>;
1853 def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off),
1854 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>;
1855 def: Pat<(HexagonAtPcrel I32:$addr),
2401 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2402 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
[all …]
/external/llvm/test/Transforms/ArgumentPromotion/
Dreserve-tbaa.ll28 ; CHECK: store i32 1, i32* %{{.*}}, align 4, !tbaa ![[I32:[0-9]+]]
29 ; CHECK: %g.val = load i32, i32* @g, align 4, !tbaa ![[I32]]
49 ; CHECK: ![[I32]] = !{![[I32_TYPE:[0-9]+]], ![[I32_TYPE]], i64 0}
/external/llvm/lib/Target/PowerPC/
DPPCLoopDataPrefetch.cpp219 Type *I32 = Type::getInt32Ty((*I)->getContext()); in runOnLoop() local
224 ConstantInt::get(I32, MemI->mayReadFromMemory() ? 0 : 1), in runOnLoop()
225 ConstantInt::get(I32, 3), ConstantInt::get(I32, 1)}); in runOnLoop()
/external/opencv3/modules/rsobjdetect/src/
Dinnerloop.cpp62 sp<const Element> e = Element::I32(rs); in innerloops()
71 sp<const Element> e3 = Element::I32(rs); in innerloops()
/external/mesa3d/src/mesa/drivers/dri/nouveau/
Dnouveau_render_t.c117 EMIT_VBO(I32, ctx, start, delta, n); in dispatch_i32()
127 EMIT_VBO(I32, ctx, start, delta, n & 1); in dispatch_i16()
/external/valgrind/none/tests/amd64/
Drcl-amd64.c5 #define I32(C) "rcrl %%ebx\n" "rcll $" #C ",%%eax\n" "rcll %%ebx\n" macro
17 asm(I32(C) : "+a"(a), "+b"(b) : /* */); \
/external/llvm/tools/llvm-stress/
Dllvm-stress.cpp449 Type *I32 = Type::getInt32Ty(BB->getContext()); in Act() local
451 Constant *CI = ConstantInt::get(I32, Ran->Rand() % (Width*2)); in Act()
454 CI = UndefValue::get(I32); in Act()
/external/llvm/test/CodeGen/AMDGPU/
D32-bit-local-address-space.ll10 ; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td219 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
231 def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
261 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
274 def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32
DX86ISelDAGToDAG.cpp1743 I32, enumerator
1970 Opc = AtomicOpcTbl[Op][I32]; in selectAtomicLoadArith()
/external/autotest/client/site_tests/firmware_TouchMTB/tests/logs/link/20130806_221321-fw_1.0.AA-robot/
Dtouch_firmware_report-link-fw_1.0.AA-complete-20140116_103340.log21428 I32
21617 I32
21993 I32
22181 I32
/external/valgrind/VEX/orig_x86/
Dmanyfp.orig6098 vex iropt: fold_Expr: no rule for: 32to1(0x1:I32)
6242 vex iropt: fold_Expr: no rule for: 32to1(0x1:I32)

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