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Searched refs:IDX (Results 1 – 25 of 25) sorted by relevance

/external/mesa3d/src/mesa/tnl/
Dt_vb_lighttmp.h31 #if IDX & LIGHT_TWOSIDE
64 #if IDX & LIGHT_TWOSIDE in TAG()
79 #if IDX & LIGHT_TWOSIDE in TAG()
93 #if IDX & LIGHT_MATERIAL in TAG()
96 #if IDX & LIGHT_TWOSIDE in TAG()
104 #if IDX & LIGHT_TWOSIDE in TAG()
165 #if IDX & LIGHT_TWOSIDE in TAG()
174 #if IDX & LIGHT_TWOSIDE in TAG()
220 #if IDX & LIGHT_TWOSIDE in TAG()
246 #if IDX & LIGHT_TWOSIDE in TAG()
[all …]
Dt_vb_light.c295 #define IDX (0) macro
299 #define IDX (LIGHT_TWOSIDE) macro
303 #define IDX (LIGHT_MATERIAL) macro
307 #define IDX (LIGHT_TWOSIDE|LIGHT_MATERIAL) macro
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_maos_verts.c86 #define IDX 0 macro
93 #define IDX 1 macro
100 #define IDX 2 macro
108 #define IDX 3 macro
116 #define IDX 4 macro
124 #define IDX 5 macro
133 #define IDX 6 macro
142 #define IDX 7 macro
152 #define IDX 8 macro
161 #define IDX 9 macro
[all …]
Dradeon_maos_vbtmp.h292 setup_tab[IDX].emit = TAG(emit); in TAG()
293 setup_tab[IDX].vertex_format = IND; in TAG()
294 setup_tab[IDX].vertex_size = sz; in TAG()
300 #undef IDX
Dradeon_state_init.c514 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ in radeonInitState() argument
523 rmesa->hw.ATOM.idx = IDX; \ in radeonInitState()
/external/liblzf/
Dlzf_c.c51 # define IDX(h) ((( h >> (3*8 - HLOG)) - h ) & (HSIZE - 1)) macro
53 # define IDX(h) ((( h >> (3*8 - HLOG)) - h*5) & (HSIZE - 1)) macro
55 # define IDX(h) ((((h ^ (h << 5)) >> (3*8 - HLOG)) - h*5) & (HSIZE - 1)) macro
71 # define IDX(h) ((h) & (HSIZE - 1))
145 hslot = htab + IDX (hval); in lzf_compress()
236 htab[IDX (hval)] = ip - LZF_HSLOT_BIAS; in lzf_compress()
241 htab[IDX (hval)] = ip - LZF_HSLOT_BIAS; in lzf_compress()
250 htab[IDX (hval)] = ip - LZF_HSLOT_BIAS; in lzf_compress()
DChanges84 - make FRST, NEXT IDX overridable if lzf_c.c is directly included
/external/skia/bench/
DVertBench.cpp28 IDX = ROW * COL * 6, enumerator
33 uint16_t fIdx[IDX];
68 SkASSERT(IDX == idx - fIdx); in VertBench()
86 fPts, nullptr, fColors, nullptr, fIdx, IDX, paint); in onDraw()
/external/mesa3d/src/glsl/
Dglsl_types.cpp432 #define IDX(c,r) (((c-1)*3) + (r-1)) in get_instance() macro
434 switch (IDX(columns, rows)) { in get_instance()
435 case IDX(2,2): return mat2_type; in get_instance()
436 case IDX(2,3): return mat2x3_type; in get_instance()
437 case IDX(2,4): return mat2x4_type; in get_instance()
438 case IDX(3,2): return mat3x2_type; in get_instance()
439 case IDX(3,3): return mat3_type; in get_instance()
440 case IDX(3,4): return mat3x4_type; in get_instance()
441 case IDX(4,2): return mat4x2_type; in get_instance()
442 case IDX(4,3): return mat4x3_type; in get_instance()
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Dbasic_operations.ll431 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
435 ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
458 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
462 ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
485 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
488 ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
511 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
514 ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
516 ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
518 ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
[all …]
Dbasic_operations_float.ll190 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
193 ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
256 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
259 ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
309 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
313 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
338 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
342 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
/external/liblzf/src/org/liblzf/
DCLZF.java139 static int IDX(int h) in IDX() method in CLZF
178 hslot = IDX (hval); in lzf_compress()
230 htab[IDX (hval)] = iidx; in lzf_compress()
234 htab[IDX (hval)] = iidx; in lzf_compress()
/external/liblzf/cs/
DCLZF.cs139 UInt32 IDX(UInt32 h) in IDX() method in LZF.NET.CLZF
178 hslot = IDX (hval); in lzf_compress()
230 htab[IDX (hval)] = iidx; in lzf_compress()
234 htab[IDX (hval)] = iidx; in lzf_compress()
/external/llvm/lib/IR/
DBasicBlock.cpp391 int IDX = PN->getBasicBlockIndex(this); in splitBasicBlock() local
392 while (IDX != -1) { in splitBasicBlock()
393 PN->setIncomingBlock((unsigned)IDX, New); in splitBasicBlock()
394 IDX = PN->getBasicBlockIndex(this); in splitBasicBlock()
/external/llvm/test/Object/
Dmacho-invalid.test35 RUN: | FileCheck -check-prefix INVALID-SECTION-IDX-SYMBOL-SEC %s
36 INVALID-SECTION-IDX-SYMBOL-SEC: getSymbolSection: Invalid section index
/external/llvm/test/CodeGen/PowerPC/
Dppc64-gep-opt.ll46 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
47 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]]
/external/llvm/test/CodeGen/AArch64/
Daarch64-gep-opt.ll52 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
53 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]]
Darm64-collect-loh.ll636 ; CHECK-NEXT: ldr q[[IDX:[0-9]+]], {{\[}}[[ADRP_REG]], [[CONSTPOOL]]@PAGEOFF]
638 ; CHECK-NEXT: tbl.16b v{{[0-9]+}}, { v{{[0-9]+}}, v{{[0-9]+}} }, v[[IDX]]
/external/llvm/test/CodeGen/AMDGPU/
Dinsert_vector_elt.ll207 ; SI: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}}
208 ; SI-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}}
/external/llvm/test/CodeGen/ARM/
Dvdup.ll374 ; CHECK: ldr r[[IDX:[0-9]+]], [r[[FP]], #4]
376 ; CHECK: vst1.64 {d{{.*}}, d{{.*}}}, [r[[SPCOPY]]:128], r[[IDX]]
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_state_init.c627 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ in r200InitState() argument
633 rmesa->hw.ATOM.idx = IDX; \ in r200InitState()
/external/mesa3d/src/gallium/drivers/nvc0/
Dnvc0_vbo.c520 BCTX_REFN(nvc0->bufctx_3d, IDX, buf, RD); in nvc0_idxbuf_validate()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp12423 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT); in LowerGlobalTLSAddress() local
12425 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX, in LowerGlobalTLSAddress()
12429 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false, in LowerGlobalTLSAddress()
12435 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale); in LowerGlobalTLSAddress()
12437 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX); in LowerGlobalTLSAddress()
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/de-DE/
Dde-DE_gl0_kpdf_mgc.pkb1898 ��y@�L�/�48-;�.��muA4XF.$ '�M�_Qohjm�i{\HILQs=N7=DOX^LSgW�lniG4:[FHJPoCGE@IDXS0�$CM�1^2��…
/external/llvm/docs/
DLangRef.rst2954 ``extractelement (VAL, IDX)``
2957 ``insertelement (VAL, ELT, IDX)``