Searched refs:ISel (Results 1 – 25 of 29) sorted by relevance
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| /external/llvm/test/CodeGen/X86/ |
| D | insertps-O0-bug.ll | 8 ; scalar load plus scalar_to_vector. This would allow ISel to match the
11 ; However, ISel can only select an INSERTPSrm if folding a load into the operand
23 ; However, ISel would fail to recognize an INSERTPSrm since load folding is
28 ; it assumes ISel to always be able to match an INSERTPSrm. This assumption is
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| D | fast-isel-x86.ll | 73 ; Fast-ISel's arg push is not here:
75 ; SDag-ISel's arg push:
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| D | promote-assert-zext.ll | 7 ; ISel doesn't yet know how to eliminate this extra zero-extend. But until
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| D | isel-optnone.ll | 35 ; Normal ISel will produce 'lea'.
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| D | lea.ll | 15 ; ISel the add of -4 with a neg and use an lea for the rest of the
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| D | addr-mode-matcher.ll | 3 ; This testcase used to hit an assert during ISel. For details, see the big
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| D | tls-addr-non-leaf-function.ll | 14 ; flag), and the ISel lowering code creating the pseudo was not informing the
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| D | fast-isel-deadcode.ll | 54 ; from Fast-ISel Phi-node handling. We should only
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| D | sse3-avx-addsub.ll | 5 ; Test ADDSUB ISel patterns.
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| D | splat-for-size.ll | 191 ; PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
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| D | ssp-data-layout.ll | 20 ; always triggers standard ISel. Run a basic test to ensure that at -O0
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | delete-node.ll | 4 ; ISel is ignoring dead nodes, though it would be preferable for
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| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-vaddd.ll | 8 ; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | udiv.ll | 19 ;The goal of this test is to make sure the ISel doesn't fail when it gets
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| D | urem.ll | 6 ; change. The goal of this test is to make sure the ISel doesn't fail
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| D | sdiv.ll | 6 ; The goal of this test is to make sure the ISel doesn't fail.
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| /external/llvm/lib/Target/Mips/ |
| D | MSA.txt | 5 optimisation, reduce the size of the ISel matcher, and reduce repetition in
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| /external/llvm/docs/ |
| D | Lexicon.rst | 125 **ISel**
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsARM.td | 25 // and return value are essentially chains, used to force ordering during ISel.
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGISel.cpp | 260 OptLevelChanger(SelectionDAGISel &ISel, in OptLevelChanger() argument
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) { in OptLevelChanger()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 1165 // ISel Patterns
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 1655 // ISel Patterns
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 1078 // the instruction definitions directly as ISel wants the address base
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| D | PPCInstrInfo.td | 1760 // the instruction definitions directly as ISel wants the address base
1834 // the instruction definitions directly as ISel wants the address base
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2873 // put the patterns on the instruction definitions directly as ISel wants
3708 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
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