Searched refs:LC1 (Results 1 – 16 of 16) sorted by relevance
| /external/valgrind/VEX/test/ |
| D | fpgames.s | 7 .LC1: label
34 pushl $.LC1
60 pushl $.LC1
68 pushl $.LC1
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| /external/llvm/test/CodeGen/ARM/ |
| D | stm.ll | 4 @"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstrin…
13 …%0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([26 x i8], [26 x i8]* @"\01LC1", i32 0, i…
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| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-relocs-01.s | 11 ld 4, .LC1@toc(2)
15 .LC1: label
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| D | ppc-reloc.s | 11 .LC1: label
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 137 def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;
160 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
250 (add LC0, SA0, LC1, SA1,
264 LC0, LC1, SA0, SA1, USR, USR_OVF];
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| D | HexagonRegisterInfo.cpp | 108 Reserved.set(Hexagon::LC1); in getReservedRegs()
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| D | HexagonHardwareLoops.cpp | 962 R == Hexagon::LC1 || R == Hexagon::SA1)) in isInvalidLoopOperation()
964 if (!IsInnerHWLoop && (R == Hexagon::LC1 || R == Hexagon::SA1)) in isInvalidLoopOperation()
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| D | HexagonInstrInfo.td | 4621 let Defs = [SA1, LC1] in
4632 Defs = [PC, LC1], Uses = [SA1, LC1] in {
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| /external/llvm/test/CodeGen/X86/ |
| D | 2008-09-29-ReMatBug.ll | 11 @"\01LC1" = internal constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1]
38 call void @foo(i8* getelementptr ([1 x i8], [1 x i8]* @"\01LC1", i32 0, i32 0)) nounwind nounwind
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| D | negate-add-zero.ll | 108 @"\01LC1" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
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| /external/clang/test/SemaCXX/ |
| D | class.cpp | 81 class LC1 { in f() class
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 131 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; in softenSetCCOperands() local
136 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
141 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
146 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
151 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
156 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
161 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
165 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
169 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : in softenSetCCOperands()
174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
[all …]
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 190 Hexagon::SA1 == R || Hexagon::LC1 == R); in isLoopRegister()
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| D | HexagonMCChecker.cpp | 45 Defs[Hexagon::LC1].insert(Unconditional); in init()
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| /external/llvm/test/Transforms/Inline/ |
| D | 2009-01-13-RecursiveInlineCrash.ll | 8 @"\01LC1" = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
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| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 565 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, in DecodeCtrRegsRegisterClass()
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