Searched refs:LHS2 (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 1068 Value *LHS, *RHS, *LHS2, *RHS2; in visitSelectInst() local
1103 if (SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor) in visitSelectInst()
1104 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(LHS),SPF2,LHS2,RHS2, in visitSelectInst()
1107 if (SelectPatternFlavor SPF2 = matchSelectPattern(RHS, LHS2, RHS2).Flavor) in visitSelectInst()
1108 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(RHS),SPF2,LHS2,RHS2, in visitSelectInst()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3780 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
3782 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
3784 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); in OptimizeVFPBrcond()
3789 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
8010 unsigned LHS2 = MI->getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
8016 .addReg(LHS2).addImm(0) in EmitInstrWithCustomInserter()
8025 .addReg(LHS2).addReg(RHS2) in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 14257 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); in Lower256IntVSETCC() local
14269 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); in Lower256IntVSETCC()
17936 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); in Lower256IntArith() local
17948 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); in Lower256IntArith()
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