| /external/vixl/examples/ |
| D | add2-vectors.cc | 57 __ Ld1(v0.V16B(), MemOperand(x0)); in GenerateAdd2Vectors() local
58 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); in GenerateAdd2Vectors() local
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| D | neon-matrix-multiply.cc | 71 __ Ld1(v4.V4S(), v5.V4S(), v6.V4S(), v7.V4S(), MemOperand(x1)); in GenerateNEONMatrixMultiply() local
73 __ Ld1(v16.V4S(), v17.V4S(), v18.V4S(), v19.V4S(), MemOperand(x2)); in GenerateNEONMatrixMultiply() local
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| /external/vixl/test/ |
| D | test-disasm-a64.cc | 2854 COMPARE(Ld1(v0.M, MemOperand(x15)), \ in TEST()
2856 COMPARE(Ld1(v1.M, v2.M, MemOperand(x16)), \ in TEST()
2858 COMPARE(Ld1(v3.M, v4.M, v5.M, MemOperand(x17)), \ in TEST()
2860 COMPARE(Ld1(v6.M, v7.M, v8.M, v9.M, MemOperand(x18)), \ in TEST()
2862 COMPARE(Ld1(v30.M, v31.M, v0.M, v1.M, MemOperand(sp)), \ in TEST()
2876 COMPARE(Ld1(v0.M, MemOperand(x15, x20, PostIndex)), \ in TEST()
2878 COMPARE(Ld1(v1.M, v2.M, MemOperand(x16, x21, PostIndex)), \ in TEST()
2880 COMPARE(Ld1(v3.M, v4.M, v5.M, MemOperand(x17, x22, PostIndex)), \ in TEST()
2882 COMPARE(Ld1(v6.M, v7.M, v8.M, v9.M, MemOperand(x18, x23, PostIndex)), \ in TEST()
2884 COMPARE(Ld1(v30.M, v31.M, v0.M, v1.M, MemOperand(sp, x24, PostIndex)), \ in TEST()
[all …]
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| D | test-assembler-a64.cc | 2919 __ Ld1(v2.V8B(), MemOperand(x17)); in TEST() local
2921 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x17)); in TEST() local
2923 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x17)); in TEST() local
2925 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), MemOperand(x17)); in TEST() local
2927 __ Ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x17)); in TEST() local
2929 __ Ld1(v20.V1D(), v21.V1D(), v22.V1D(), v23.V1D(), MemOperand(x17)); in TEST() local
2975 __ Ld1(v2.V8B(), MemOperand(x17, x23, PostIndex)); in TEST() local
2976 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x18, 16, PostIndex)); in TEST() local
2977 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x19, 24, PostIndex)); in TEST() local
2978 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), in TEST() local
[all …]
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| /external/llvm/test/Transforms/LoopVectorize/AArch64/ |
| D | reduction-small-size.ll | 141 ; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <8 x i8>
142 ; CHECK: zext <8 x i8> [[Ld1]] to <8 x i16>
|
| /external/vixl/src/vixl/a64/ |
| D | macro-assembler-a64.h | 2524 void Ld1(const VRegister& vt, in Ld1() function
2530 void Ld1(const VRegister& vt, in Ld1() function
2537 void Ld1(const VRegister& vt, in Ld1() function
2545 void Ld1(const VRegister& vt, in Ld1() function
2554 void Ld1(const VRegister& vt, in Ld1() function
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