| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoVector.td | 305 (LoReg (A2_vaddub (Zext64 $Rs), (Zext64 $Rt)))>;
310 (LoReg (A2_vsubub (Zext64 $Rs), (Zext64 $Rt)))>;
316 (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>;
318 (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>;
389 (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
407 (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
411 (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
428 (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)),
434 (vmpyh (LoReg $Rs), (LoReg $Rt)))>;
438 (vmpyh (LoReg (S2_vsxtbh $Rs)), (LoReg (S2_vsxtbh $Rt))))>;
[all …]
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| D | HexagonCopyToCombine.cpp | 640 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local
651 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
659 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
666 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
674 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
681 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
739 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local
749 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
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| D | HexagonInstrInfo.td | 30 def LoReg: OutPatFrag<(ops node:$Rs),
3215 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3639 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>;
3640 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>;
3641 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>;
3644 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
3645 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
3646 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
4322 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4957 (A2_sxtw (LoReg DoubleRegs:$src1))>;
[all …]
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| D | HexagonFrameLowering.cpp | 695 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg); in insertCFIInstructionsAt() local
697 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
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| D | HexagonInstrInfoV5.td | 794 (LoReg (F2_conv_df2d_chop F64:$src1))>,
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| D | HexagonIntrinsics.td | 683 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
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| D | HexagonInstrInfoV4.td | 3843 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2424 unsigned LoReg; in Select() local
2427 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; in Select()
2428 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; in Select()
2429 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; in Select()
2430 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; in Select()
2433 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
2473 unsigned SrcReg, LoReg, HiReg; in Select() local
2478 SrcReg = LoReg = X86::AL; HiReg = X86::AH; in Select()
2482 SrcReg = LoReg = X86::AX; HiReg = X86::DX; in Select()
2486 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 286 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
303 std::swap(LoReg, HiReg); in expandBuildPairF64()
304 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
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| D | MipsSEInstrInfo.cpp | 629 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
658 .addReg(LoReg); in expandBuildPairF64()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8757 unsigned LoReg = MI->getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
8761 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
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